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Paul2
Newbie
Newbie
406 Views
Registered: ‎01-28-2021

Spartan 7 Eval board (EK-S7-SP701-G) - FPGA programming (need help)

Hello,

I bought a Xilinx FPGA Spartan 7 evaluation board EK-S7-SP701-G and I have difficulty to program the FPGA.

FPGA mounted on the board is XC7S100 (FGGA676ABX1913).

After a few trials with the bitstream of the project, we finally created a very simple design to check if we are using well the environment, and it didn't worked, so I need your support.

This simple design is connection of the 30MHz default clock to an IO.

VHDL:

vhdl.jpg

VIVADO settings:

capture1.jpg

schematics is OK :

schematics.jpg

Mapping of the signals : I expect to measure the clock on the pin G24 of the connector J21 (FMC LPC)

mapping.JPG

We clicked on GENERATE BITSTREAM.

 

Now, we would like to program the FPGA using the XILINX Platorm Cable USB II (connected on J3 connector).

Vivado lab edition recognizes the board :

program_FPGA.JPG

We assigned the .bit file and then programmed the FPGA.

Unfortunately, once the programming is done, there is no clock on pin G24 of connector J21.

Do you see some mistakes here ? What could you recommend me to do to solve this issue ? Did we miss something ?

thanks a lot in advance and have a nice day.

Best regards

Paul

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4 Replies
drjohnsmith
Teacher
Teacher
394 Views
Registered: ‎07-09-2009

I don't know this particular board 

  but most ( ? All ? ) of the xilinx boards come with a guide and a reference design for you to use as a starting point.

 Have you tried that 

using a known good design is a great way to prove the system, 

     and then make changes to / learn from , 

          and if you get a problem, its always great to return to as a confidence builder

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Paul2
Newbie
Newbie
389 Views
Registered: ‎01-28-2021

Hello drjohnsmith,

thanks a lot for your reply. 

At first we tried to program the FPGA board with a vhdl we were using on a virtex 4 evaluation board.

However with Virtex 4 evaluation board we converted the .bit to a .mcs to program a configuration memory xcf32p that was mounted on the board.

I don't have a lot of knowledge in this field, but if I have well understood there is no configuration memory on the Spartan 7 evaluation board, so I assume that I have to program the target with the .bit file directly.

That's why we tried with the simplest vhdl : if we are not able to program this one, I think a more complicated one will not work.

thanks again and have a nice day.

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drjohnsmith
Teacher
Teacher
359 Views
Registered: ‎07-09-2009

A bit file is unique to each FPGA type,

   rather like cars and fuel, you cant; put diesel into a petrol car.

So there is no way the V4 file will work in a spartan 7 

Re programming, 

   FPGAs , generally have no permanent configuration memory in them, they need re programming at each power up 

      on a board, this configuration fiel is normaly in a flash device, that you cna program via the xilixn tools.

Regarding your code,

   you have vhdl, have you the .cgf file to set up the pins and the timing ?

     with out it , you wont get much..

Have you looked at the boards page

https://www.xilinx.com/products/boards-and-kits/sp701.html

there are a whole lot of tutorials on there for you to follow 

    after you have done them all you will be fairly good at the system,

Im sorry

  but from the sounds of things, you have a fairly long road to go down here.

I'm not certain the forums is the place that you can get all that information, I could be wrong, but its just a thought.

 

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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bruce_karaffa
Scholar
Scholar
328 Views
Registered: ‎06-21-2017

You have two critical warnings.  What are they?  Your IO type is LVCMOS18.  Is Vadj set to 1.8V on your board?

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