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Explorer
Explorer
6,692 Views
Registered: ‎05-21-2009

Specifying pin location

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Hi guys,

 

I'm not really sure where to start looking, but say I have a "for generate"-loop and each instance of the loop needs access to physical pins on the FPGA. Is it possible to add constraints to place the pins relative to the instance placed? I don't want to physically specify the location of each instance. Sorry if I am missing the necessary terminology to describe the problem, but I hope you understand.

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Xilinx Employee
Xilinx Employee
8,970 Views
Registered: ‎07-01-2008

Re: Specifying pin location

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Vivado and ISE (7-series only) enforce a DRC rule that all IO ports must be LOC constrained. So in the end you will need to LOC constrain the ports rather than using other means to guide the placement.

 

IO components can be part of an RPM macro but there's not much point when you have to constrain the pins anyway and the placement tools automatically handle the relative placement of ILOGIC/OLOGIC BELs. The main use case for including IO logic in an RPM macro would be to control the placement of related logic in the fabric.

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Contributor
Contributor
6,687 Views
Registered: ‎04-22-2013

Re: Specifying pin location

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hello

I used during my training session the Virtex 5 ml with 501 EDK ISE SDK version 10.1 and after créeation my embedded system by default and did its implementation using ise and after I had created the project "hello world "
but on hyperterminal I do not see the message I see in tera term malgrès other character that is set with the speed (9600,8, none, 1, none)

 

 

 

 

 

plese  if possible help me overcome this problem 

trying to debug a program with the MicroBlaze
Hi

I use the environment Xinx (edk, ise ..) version 10.1 and when I type in "dow testapp_peripheral / executable.elf" xmd console and even the test of memory, I oubtient this:

xmd% dow testapp_memory/executable.elf
system reset downloading....DONE
downloading program--testapp_memory/executable.elf
section ,.vector.reset:0*00000000-0*00000007
section ,.vector. sw_exception:0*000000008-0*00000000f
.
.
.
.
.
.
.
.
section ,.stack:0*8a307348-0*8a309347
setting PC with Program start Adress 0*00000000
xmd% run
info: Processor Started.Type "stop" to stop processor
RUNNNING>xmd% info: cable is locked.Retrying....
info: cable is locked.Retrying....
info: cable is locked.Retrying....
info: cable is locked.Retrying....
info: cable is locked.Retrying....


Does there anyone who can help me?
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Explorer
Explorer
6,682 Views
Registered: ‎05-21-2009

Re: Specifying pin location

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Please don't hi-jack my thread. Create your own.

Instructor
Instructor
6,661 Views
Registered: ‎08-14-2007

Re: Specifying pin location

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Are you saying that you want the pins for each instance to somehow have the same relative positions with respect to one another?  I'm not sure if this is possible, because the IOB's are not grid-based like other fabric components that you can generally use RLOC constraints for.

-- Gabor
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Explorer
Explorer
6,656 Views
Registered: ‎05-21-2009

Re: Specifying pin location

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Hi Gabor,

 

That is exactly what I wanted to know. So there is no RLOC constraint for physical pins? I saw a post somewhere on the forums about a guy placing constraints for "generate"-loops. Maybe I can use a similar approach. Will have to search for it though. Thanks for your help!

 

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Instructor
Instructor
6,646 Views
Registered: ‎08-14-2007

Re: Specifying pin location

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The only other thing I can think of is to try to use RLOC on the input or output registers instead of the

pin.  This might depend on the device family, but for example Spartan 6 has ILOGIC and OLOGIC

components on a grid.  I believe LOCing the register to a particular ILOGIC or OLOGIC site would

force the use of a particular package pin.

-- Gabor
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Xilinx Employee
Xilinx Employee
8,971 Views
Registered: ‎07-01-2008

Re: Specifying pin location

Jump to solution

Vivado and ISE (7-series only) enforce a DRC rule that all IO ports must be LOC constrained. So in the end you will need to LOC constrain the ports rather than using other means to guide the placement.

 

IO components can be part of an RPM macro but there's not much point when you have to constrain the pins anyway and the placement tools automatically handle the relative placement of ILOGIC/OLOGIC BELs. The main use case for including IO logic in an RPM macro would be to control the placement of related logic in the fabric.

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Explorer
Explorer
6,631 Views
Registered: ‎05-21-2009

Re: Specifying pin location

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I understand. Thanks for all your help guys! Much appreciated!

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