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Explorer
Explorer
669 Views
Registered: ‎01-02-2012

Sporadic "EXCEPTION_ACCESS_VIOLATION" crashes & "[Place 30-488] Failed to commit 9 instances" errors

Dear experts,

I am trying to place some registers into a pblock, which is definetely sufficient for them:

create_pblock pblock_for_s2_p1_rx_regs
resize_pblock pblock_for_s2_p1_rx_regs   -add SLICE_X82Y200:SLICE_X83Y203

add_cells_to_pblock pblock_for_s2_p1_rx_regs [get_cells [list {slot[2].if_inst/front_end/dual_rgmii.bridge[1].inst/gmii2rgmii_inst/rx_regs.gmii_rxd_*} \
                                                              {slot[2].if_inst/front_end/dual_rgmii.bridge[1].inst/gmii2rgmii_inst/rx_regs.gmii_rx_c*} ]]

However, I get often (but not always, almost every second run) "[Place 30-488] Failed to commit 9 instances" errors!  

[Place 30-488] Failed to commit 9 instances:
slot[2].if_inst/front_end/dual_rgmii.bridge[1].inst/gmii2rgmii_inst/rx_regs.gmii_rx_ctl_f_reg_reg with block Id: 44524 (FF) at SLICE_X53Y195
slot[2].if_inst/front_end/dual_rgmii.bridge[1].inst/gmii2rgmii_inst/rx_regs.gmii_rx_ctl_r_reg_reg with block Id: 44525 (FF) at SLICE_X0Y223
slot[2].if_inst/front_end/dual_rgmii.bridge[1].inst/gmii2rgmii_inst/rx_regs.gmii_rxd_reg_reg[0] with block Id: 44526 (FF) at SLICE_X47Y211
slot[2].if_inst/front_end/dual_rgmii.bridge[1].inst/gmii2rgmii_inst/rx_regs.gmii_rxd_reg_reg[1] with block Id: 44527 (FF) at SLICE_X158Y166
slot[2].if_inst/front_end/dual_rgmii.bridge[1].inst/gmii2rgmii_inst/rx_regs.gmii_rxd_reg_reg[2] with block Id: 44528 (FF) at SLICE_X92Y190
slot[2].if_inst/front_end/dual_rgmii.bridge[1].inst/gmii2rgmii_inst/rx_regs.gmii_rxd_reg_reg[3] with block Id: 44529 (FF) at SLICE_X163Y166
slot[2].if_inst/front_end/dual_rgmii.bridge[1].inst/gmii2rgmii_inst/rx_regs.gmii_rxd_reg_reg[4] with block Id: 44530 (FF) at SLICE_X36Y233
slot[2].if_inst/front_end/dual_rgmii.bridge[1].inst/gmii2rgmii_inst/rx_regs.gmii_rxd_reg_reg[5] with block Id: 44531 (FF) at SLICE_X134Y186
slot[2].if_inst/front_end/dual_rgmii.bridge[1].inst/gmii2rgmii_inst/rx_regs.gmii_rxd_reg_reg[6] with block Id: 44532 (FF) at SLICE_X134Y186

 

"DONT_TOUCH" attribute of these registers is set in the VHDL and *_opt.dcp is attached here

What am I missing? I am doing this for several other registers in the design and only these create this issue. They are behind the MGT region and routing from IO pads to there is tricky, but why does placement (sometimes) fail? 

Furthermore, I get "EXCEPTION_ACCESS_VIOLATION" errors time to time at various stages. Using Vivado 2018.3 for 200K Artix-7.

Your help is very much appreciated.

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5 Replies
Xilinx Employee
Xilinx Employee
642 Views
Registered: ‎05-08-2012

Re: Sporadic "[Place 30-488] Failed to commit 9 instances" errors

Hi @xil_azdem.

I would check the messaging in the log before the failure. Is there any messages relating the pblock that indicate possible issues leagalizing placement?

Also, what is utilization within the pblock "report_utilization -pblocks [get_pblocks pblock_for_s2_p1_rx_regs]"


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Explorer
Explorer
610 Views
Registered: ‎01-02-2012

Re: Sporadic "[Place 30-488] Failed to commit 9 instances" & "EXCEPTION_ACCESS_VIOLATION" errors

Hi @marcb

Thank you very much for the reply.

I see this warning message:
[Place 30-769] High register utilization is forcing place_design to place up to 8 registers per slice in pblock PBLOCK: pblock_for_s2_p1_rx_regs which may impact placement success and/or routing congestion.

But, I still do not understand, why I get this only for this pblock. I have other (even 50% smaller) plocks, placing same amount of registers to them is not creating any warnings (see the second utilization report below).  

1.

report_utilization -pblocks [get_pblocks pblock_for_s2_p1_rx_regs]
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
--------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3_AR71898 (win64) Build 2405991 Thu Dec  6 23:38:27 MST 2018
| Date         : Mon Feb 11 09:21:33 2019
| Host         : PC-001-80-1 running 64-bit Service Pack 1  (build 7601)
| Command      : report_utilization -pblocks [get_pblocks pblock_for_s2_p1_rx_regs]
| Design       : elog_a7_top
| Device       : 7a200tifbv676-1L
| Design State : Synthesized
--------------------------------------------------------------------------------------------

Utilization Design Information

Table of Contents
-----------------
1. Pblock Summary
2. Clock Region Statistics
3. Slice Logic
3.1 Summary of Registers by Type
4. Memory
5. DSP
6. IO and GT Specific
7. Clocking
8. Specific Feature
9. Primitives
10. Black Boxes
11. Instantiated Netlists

1. Pblock Summary
-----------------

+-------+--------------------------+-------+-------------------+-----------------+----------------+
| Index |          Parent          | Child | EXCLUDE_PLACEMENT | CONTAIN_ROUTING | SLR(s) Covered |
+-------+--------------------------+-------+-------------------+-----------------+----------------+
| 1     | pblock_for_s2_p1_rx_regs |       |                 0 |               0 |           SLR0 |
+-------+--------------------------+-------+-------------------+-----------------+----------------+


2. Clock Region Statistics
--------------------------

+-------------+--------------------+
| CLOCKREGION | Pblock Sites in CR |
+-------------+--------------------+
| X0Y4        |            100.00% |
+-------------+--------------------+


3. Slice Logic
--------------

+-------------------------+--------+-------+--------------+------+-------+-----------+-------+
|        Site Type        | Parent | Child | Non-Assigned | Used | Fixed | Available | Util% |
+-------------------------+--------+-------+--------------+------+-------+-----------+-------+
| Slice LUTs*             |      0 |     0 |            0 |    0 |     0 |        32 |  0.00 |
|   LUT as Logic          |      0 |     0 |            0 |    0 |     0 |        32 |  0.00 |
| Slice Registers         |     20 |     0 |            0 |   20 |     0 |        64 | 31.25 |
|   Register as Flip Flop |     20 |     0 |            0 |   20 |     0 |        64 | 31.25 |
|   Register as Latch     |      0 |     0 |            0 |    0 |     0 |        64 |  0.00 |
| F7 Muxes                |      0 |     0 |            0 |    0 |     0 |        16 |  0.00 |
| F8 Muxes                |      0 |     0 |            0 |    0 |     0 |         8 |  0.00 |
+-------------------------+--------+-------+--------------+------+-------+-----------+-------+
* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.


3.1 Summary of Registers by Type
--------------------------------

+-------+--------------+-------------+--------------+
| Total | Clock Enable | Synchronous | Asynchronous |
+-------+--------------+-------------+--------------+
| 0     |            _ |           - |            - |
| 0     |            _ |           - |          Set |
| 0     |            _ |           - |        Reset |
| 0     |            _ |         Set |            - |
| 0     |            _ |       Reset |            - |
| 0     |          Yes |           - |            - |
| 0     |          Yes |           - |          Set |
| 0     |          Yes |           - |        Reset |
| 0     |          Yes |         Set |            - |
| 20    |          Yes |       Reset |            - |
+-------+--------------+-------------+--------------+


4. Memory
---------

+-----------+--------+-------+--------------+------+-------+-----------+-------+
| Site Type | Parent | Child | Non-Assigned | Used | Fixed | Available | Util% |
+-----------+--------+-------+--------------+------+-------+-----------+-------+
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1


5. DSP
------

+-----------+--------+-------+--------------+------+-------+-----------+-------+
| Site Type | Parent | Child | Non-Assigned | Used | Fixed | Available | Util% |
+-----------+--------+-------+--------------+------+-------+-----------+-------+


6. IO and GT Specific
---------------------

+-----------+--------+-------+--------------+------+-------+-----------+-------+
| Site Type | Parent | Child | Non-Assigned | Used | Fixed | Available | Util% |
+-----------+--------+-------+--------------+------+-------+-----------+-------+


7. Clocking
-----------

+-----------+--------+-------+--------------+------+-------+-----------+-------+
| Site Type | Parent | Child | Non-Assigned | Used | Fixed | Available | Util% |
+-----------+--------+-------+--------------+------+-------+-----------+-------+


8. Specific Feature
-------------------

+-----------+--------+-------+--------------+------+-------+-----------+-------+
| Site Type | Parent | Child | Non-Assigned | Used | Fixed | Available | Util% |
+-----------+--------+-------+--------------+------+-------+-----------+-------+


9. Primitives
-------------

+----------+------+---------------------+
| Ref Name | Used | Functional Category |
+----------+------+---------------------+
| FDRE     |   20 |        Flop & Latch |
+----------+------+---------------------+


10. Black Boxes
---------------

+----------+------+
| Ref Name | Used |
+----------+------+


11. Instantiated Netlists
-------------------------

+----------+------+
| Ref Name | Used |
+----------+------+

 2.

report_utilization -pblocks [get_pblocks pblock_for_s2_p0_rx_regs]

...
3. Slice Logic
--------------

+-------------------------+--------+-------+--------------+------+-------+-----------+-------+
|        Site Type        | Parent | Child | Non-Assigned | Used | Fixed | Available | Util% |
+-------------------------+--------+-------+--------------+------+-------+-----------+-------+
| Slice LUTs*             |      0 |     0 |            0 |    0 |     0 |        16 |  0.00 |
|   LUT as Logic          |      0 |     0 |            0 |    0 |     0 |        16 |  0.00 |
|   LUT as Memory         |      0 |     0 |            0 |    0 |     0 |         8 |  0.00 |
| Slice Registers         |     20 |     0 |            0 |   20 |     0 |        32 | 62.50 |
|   Register as Flip Flop |     20 |     0 |            0 |   20 |     0 |        32 | 62.50 |
|   Register as Latch     |      0 |     0 |            0 |    0 |     0 |        32 |  0.00 |
| F7 Muxes                |      0 |     0 |            0 |    0 |     0 |         8 |  0.00 |
| F8 Muxes                |      0 |     0 |            0 |    0 |     0 |         4 |  0.00 |
+-------------------------+--------+-------+--------------+------+-------+-----------+-------+

 

Furthermore, I get "EXCEPTION_ACCESS_VIOLATION" errors time to time: Most of the time I can pass it using the workaround mentioned at AR# 71509, which blongs to 2018.1 version.

 

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Xilinx Employee
Xilinx Employee
576 Views
Registered: ‎05-08-2012

Re: Sporadic "[Place 30-488] Failed to commit 9 instances" & "EXCEPTION_ACCESS_VIOLATION" errors

Hi @xil_azdem.

The problem is the number of control sets going into this region. This portion of the device is narrow. It is 1 CLB vertically (2 SLICEs side by side are contained within the same CLB). There are 3 control sets driving this region (report_control_sets -cells [get_cells <>] -verbose). Using ECO commands, I reduced the control sets to 2, and placement was successful. An alternative to reducing the control sets would be to add CLBs to the bottom of the pblock.


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narrow.png
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Explorer
Explorer
547 Views
Registered: ‎01-02-2012

Re: Sporadic "[Place 30-488] Failed to commit 9 instances" & "EXCEPTION_ACCESS_VIOLATION" errors

Hi @marcb,

thanks again for the analysis.

Unfortunately, I can not move the pblock below: Registers are clocked through BUFH and right below is another clock region. (In case you meant that with "... add CLBs to the bottom of the pblock")

Why do I have problem with control sets? These registers do not have either (sync/async) reset or clock enables...

Can you please elaborate on the purpose and usage of ECO commands? I am new to this.  

 

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Xilinx Employee
Xilinx Employee
518 Views
Registered: ‎05-08-2012

Re: Sporadic "[Place 30-488] Failed to commit 9 instances" & "EXCEPTION_ACCESS_VIOLATION" errors

Hi @xil_azdem.

The ECO test shows that if the logic in the pblock has 2 control sets, this is a feasable placement, but not with 3 control sets. A control set is common to a CLB (2 side by side SLICE sites in earlier image), and the pblock is set to a rectange 1 CLB wide. If there is not a significant performance benifit, I would not suggest restricting this logic to an area with reduced resources.


-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

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Don’t forget to reply, kudo, and accept as solution.
---------------------------------------------------------------------------------------------
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