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lznger88
Visitor
Visitor
2,790 Views
Registered: ‎04-18-2010

Square Root Troubles

Hey all,

 

I am using a C code

 x= 11;
 v = x;

    for i = 1 : 10
      v = ( v + ( x / v ) ) / 2
    end

 

 %Call number x, and our estimate of its square root will be called V;
     %Start off by setting V to be 1;
     %Average V and X/ V, is our new estimate;
     %Repeat process , i'd say about 5 times;
     %output X,
 

 

to implement using simulink with Xilinx blocks. I know how the code works and what it should do but I dont understand how to the answer to the first estimate loop backs into the divisor until i get the right answer to the number I am trying to calculate. I can get the correct square root answer if I use a constant value but it is there a way to get the value outputted from the shift register to loop back into the divisor until the correct answer is obtain. How do I go about this, do I use a Mux cause i've tried but maybe i dont know how to connect it properly. I

 

here is what i have done so far... (attached)

 

Thank you

 

Steve

 

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john.h
Explorer
Explorer
2,760 Views
Registered: ‎02-27-2010

If you need an output every cycle, you'll need to pipeline your results.

 

If you can load, crunch, and output on just one value over many cycles, you just need to have a load and read after 10 cycles:

 

if( load )  v <= (x+1)/2;  else  v <= (v+(x/v))/2;

 

However, the biggest problem you may be facing is that division.  Since division is long and involved, you probably need to impliment a divider IP core or use a reciprocal lookup to determine 1/v and multiply.

 

Many people have wondered how to do division by a variable in FPGAs and gotten stuck.  If you search for division in Verilog or VHDL you'll find there's a lot of resources out there and different ways to approach the problem.

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