05-03-2017 01:26 PM
As I said in the title I have two finite state machines and one of them will run the other multiple times (it is two for now). Plan is having a signal which is 1 through the 2nd FSM until it arrives to initial state back. Then initial state will drive the "flag" signal 0. Then the first FSM will go to the second state and run the 2nd FSM once more. In the end both will be back to the initial state until another flag start the first "controller" FSM.
What I observed is second one runs only for once. I can see the flag becomes 1 and then 0. So I thought it is working but for once.
Thanks in advance
05-03-2017 02:12 PM
@macellan85 to be frank, I don't see why you can't code and debug this in RTL if you can type what you want. There is no challenge here; just code the FSMs as you describe and run them under the simulator to see what you missed. You are simulating your design, yes? If you are putting it on hardware after it passes synthesis, you deserve what you get ;-)
05-03-2017 03:01 PM - edited 05-03-2017 03:37 PM
Thank you @muzaffer for the answer.
Actually I'm not using the simulator. I tried it during the first days when I started to do FPGA design. Then I had difficulty to declare the clock and now directly checking the output on a scope. I want to do it as well but for now I can do some basic stuff this way. If you have any useful doc. etc makes understanding the simulation issues little bit easier please let me know.
On the other hand, I don't know either why it doesn't work :) since it is not that much complicated. I think I miss something and another eye can identify this, hopefully.
I attached the vhd designs. They are connected to some other modules as I said before. Little bit detail of the process:
flag0 = 1 starts FSM1
FSM1 generates flag1 = 1 which starts another process to generate a definite width pulse (P) to start FSM2. P=0 much before flag2 and resets flag1=0.
FSM2 generates flag2 =1 during operation. In the end it goes back to flag2=0
flag2=0 change state of FSM1 ST1 to ST2 , flag1=1, and FSM2 process again through P.
FSM1 goes back to ST0 flag1=0
Thanks in advance
05-03-2017 05:32 PM
@macellan85 I'd point you to this amazing new invention called the Internet and search engines:
05-04-2017 04:02 AM
Thank you for introducing this amazing invention @muzaffer but I need advice to solve my question above :)
Instead of observing the signals on the test bench window, I can see the real outputs. They just don't behave how I want them !
Question: What can be the problem?
05-04-2017 06:55 AM
At the risk of causing you to be unhappy (which it seems you are), I can only make a couple of suggestions.
One: the architecture you have chosen is odd. Regardless of how you think it is a good solution, a simple state machine with as many states as required is a better approach.
Two: when it doesn't work, you need to debug it. I suggest creating a testbench, and simulating it to find your bug.
Lastly, although I am also tempted to provide a sarcastic answer to questions such as yours, I as a Xilinx employee must remind myself you are the customer, and by definition "are always right." Even a new student buying a Digilent board in some small way pays my salary. Thank you.
Marking @muzaffer 's reply as 'abuse' did get my attention. But, I would be too hard on him, as he answers many questions in the forums and is one of the top responders. And, the internet is a great resource.
05-05-2017 10:37 AM
Do the two FSMs run at the same frequency or different frequencies?
I'm a bit confused by this state in FSM1:
when ST_FIRST_PART =>
s_DO_Data_Part <= "01110111";
s_DO_Set_flag <= '1' ;
if ( s_DO_Period_Flag = '0' ) AND ( s_DO_Data_Sent_progress_flag = '0' ) then
NEXT_STATE <= ST_SECOND_PART ;
s_DO_Set_flag <= '0' ;
NEXT_STATE <= ST_FIRST_PART ;
end if ;
I see you are trying to assert s_DO_Set_flag but if the if statement evaluates FALSE then s_DO_Set_flag will deassert in the same clock cycle. That is, the assignment will be overridden. So, if the conditions required to evaluate the if statement TRUE are not present as the FSM enters the ST_FIRST_PART state, then s_DO_Set_flag will never assert.
It would be better to put the s_DO_Set_flag assertion in the ST_IDLE state as you transition to the ST_FIRST_PART state.
Some other pointers:
Don't use ieee.std_logic_unsigned and ieee.numeric_std together. Just use ieee.numeric_std.
Fully synchronous processes only need the clock on the sensitivity list.
You positively must learn to simulate. You will save yourself so much time and debug pain. You've already seen how long it takes to debug, by your own admission, not a complicated design.
05-08-2017 12:15 AM
i think I shall reply to myself now that I see what is trying to happen a little better.
The FSM1 is using the ST_FIRST_PART as a wait state until some other event happens, right? If this is true then ignore what i wrote as it isn't correct at all.
Back to the drawing board for me!
The first question is still valid though - are the two FSMs being clocked by a common clock?