06-25-2013 05:45 AM
06-25-2013 08:19 AM
Try LOC'ing your BUFGMUX components, instead of the net. I would inspect the successfully routed design in FPGA editor and look for all of the BUFGMUXes being driven by other BUFGMUXes or input pins. Lock those down in your UCF to the successfully routed locations.
Can you use a DCM somewhere in there? You might see some intermittent behavior without one. Propagation delays can change slightly based on the net fanout and the particular routing topology. If you absolutely can't use a DCM, I would LOC down every component and NET in that schematic.
07-01-2013 10:21 PM
The problem with these clock placement messages is that they aren't able to tell you why a successfull placement wasn't found, they are only able to describe what's wrong with the failed placement. In this case an IOB and BUFGMUX are not placed correctly relative to each other. I suspect that this has to do with a conflicting requirement on the BUFGMUX. This might be the requirement in Spartan-6 that only BUFGMUX sites from the upper tier of BUFGMUX sites can drive other BUFGMUX sites.
07-02-2013 06:57 AM
The Error message is essentially correct. As Bret states you must use one of the top 8 BUFGs to drive any input other than the .SR pin or .CLK pins or in this case the BUFGMUX input. The input to a BUFG is not a CLK or SR pin so one of the top 8 BUFGs must be used to drive the input to the 2nd cascased BUFG.
The error message is stating that Clock Component BUFG XLNX2 (not the pad) is placed at BUFGMUX_X3Y8. This is a required placement since it is one of the top 8 BUFGMUX sites and is driving a 2nd BUFGMUX. Now the error is telling you that you have Location Constrained your Clock Input to a site that is not routable to a BUFGMUX in the top half of the device.
For this to route you MUST place this clock in either Bank0 or Bank1 so that the dedicated path from the GCLK PAD to the BUFGMUX can be used.