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Observer
Observer
3,992 Views
Registered: ‎11-30-2010

Strange errors while pin lock for Spartan-6

Hi! I try to make complex design using chained BUFGMUX's in Spartan-6. Due to limited clocking resources of S6, i often get non-routable design. The first problem is clocking-related error messages generated by ISE14.4 for S6 are quite not meaningful and even often not related to part of schematic i was changed recently. But i can live with this, using only the fact that error(s) are exist or not. But more important, i notice the tools sometimes can't route design that is definetely routable. I prepare simple testcase, take only some clock nets from my main design (please see photo): When i lock the net XLXN_17 at P70, error arrives. The error text (seen on photo) is not related at all with this pin, but as i mentioned before, it is not really a problem. BUT, when i lock that net to BANK2, design is routable, and this net becomes exactly P70! What i can do with this? I am wrong somewhere? The part i use is XC6SLX9-2TQG144.
P.S. Also quite strange Warning (not error, but this simple design should be precisely correct) is 'Xst:2676 - LOC constraint BANK1 of signal <XLXN_4> is already used by <XLXN_3>, it will be ignored'. It really looks like bug...
 
Thank you!
 
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Explorer
Explorer
3,982 Views
Registered: ‎04-09-2008

Try LOC'ing your BUFGMUX components, instead of the net. I would inspect the successfully routed design in FPGA editor and look for all of the BUFGMUXes being driven by other BUFGMUXes or input pins. Lock those down in your UCF to the successfully routed locations.

 

Can you use a DCM somewhere in there? You might see some intermittent behavior without one. Propagation delays can change slightly based on the net fanout and the particular routing topology. If you absolutely can't use a DCM, I would LOC down every component and NET in that schematic.

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Scholar
Scholar
3,950 Views
Registered: ‎07-01-2008

The problem with these clock placement messages is that they aren't able to tell you why a successfull placement wasn't found, they are only able to describe what's wrong with the failed placement. In this case an IOB and BUFGMUX are not placed correctly relative to each other. I suspect that this has to do with a conflicting requirement on the BUFGMUX. This might be the requirement in Spartan-6 that only BUFGMUX sites from the upper tier of BUFGMUX sites can drive other BUFGMUX sites.

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Xilinx Employee
Xilinx Employee
3,941 Views
Registered: ‎06-20-2008

The Error message is essentially correct. As Bret states you must use one of the top 8 BUFGs to drive any input other than the .SR pin or .CLK pins  or in this case the BUFGMUX input.  The input to a BUFG is not a CLK or SR pin so one of the top 8 BUFGs must be used to drive the input to the 2nd cascased BUFG. 

 

The error message is stating that Clock Component BUFG XLNX2 (not  the pad) is placed at BUFGMUX_X3Y8.  This is a required placement since it is one of the top 8 BUFGMUX sites and is driving a 2nd BUFGMUX.  Now the error is telling you that you have Location Constrained your Clock Input to a site that is not routable to a BUFGMUX in the top half of the device.  

For this to route you MUST place this clock in either Bank0 or Bank1 so that the dedicated path from the GCLK PAD to the BUFGMUX can be used.