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Explorer
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Registered: ‎02-24-2016

Sub-optimal placement for a BUFG-BUFG cascade pair -> how to solve?

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Hi All,

 

I've got the [Place 30-120] Sub-optimal placement for a BUFG-BUFG cascade pair error.

 

I understand that the error occurs because BUFG cannot be cascaded... 

 

Please see below the "problematic" logic. As you could see, clock mux's output is connected to the clock gated cell. I guess this is the problem. So, how to solve? The clock mux's output drives several inst0 and inst1 without any clock gating, but the same clock should be gated for inst2 (see the picture below).

 


 

clk_mux.jpg


 

 

How to implement this logic without placement errors?

 

Thank you!

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Xilinx Employee
Xilinx Employee
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Registered: ‎05-07-2015

Re: Sub-optimal placement for a BUFG-BUFG cascade pair -> how to solve?

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HI @dmitry1417

 

Open synthesized design, In the netlist tab, select the BUGMUX  primitve and drag it on the device view , place it some BUFG location at the center of the device.
Do the same  for the BUFGCE instance and place it on BUFG location adjacent to the BUFGMUX location. 
when you save , respective LOC constraints will  be written into the xdc file.

Thanks
Bharath
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Xilinx Employee
Xilinx Employee
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Registered: ‎09-20-2012

Re: Sub-optimal placement for a BUFG-BUFG cascade pair -> how to solve?

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Hi @dmitry1417

 

I assume that you are using 7 series device.

 

If only 2 BUFG's are cascaded, the tool should be able to find optimal locations for them. What are the drivers of BUFMUX?

Thanks,
Deepika.
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Explorer
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Re: Sub-optimal placement for a BUFG-BUFG cascade pair -> how to solve?

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yes, this is zynq 7020

 

clk0 and clk1 are input pins, clk_g also goes to output pin of the device

 

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Moderator
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Registered: ‎01-16-2013

Re: Sub-optimal placement for a BUFG-BUFG cascade pair -> how to solve?

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@dmitry1417,

 

There are specific rules which needs to be followed when using cascaded BUFG. Please check page number 35 in below 7 series clocking resource user guide:

http://www.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdf

 

Make sure you are not violating any rule.

Can you check what other loads are driven by clk?

 

--Syed

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Xilinx Employee
Xilinx Employee
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Registered: ‎05-07-2015

Re: Sub-optimal placement for a BUFG-BUFG cascade pair -> how to solve?

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HI @dmitry1417

 

How many BUFG are there in your design.
Can you try LOC the BUFGMUX and BUFGCE to adjacent locations..
LOC those BUFGs to the same half of the device  in which the IO bank of the clk0 and clk1 input ports is present

Thanks
Bharath
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Explorer
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Registered: ‎02-24-2016

Re: Sub-optimal placement for a BUFG-BUFG cascade pair -> how to solve?

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How can I LOC the BUFGs? Thank you  

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Xilinx Employee
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Registered: ‎09-20-2012

Re: Sub-optimal placement for a BUFG-BUFG cascade pair -> how to solve?

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Hi @dmitry1417

 

You can use below constraint

 

set_property LOC BUFGCTRL_XxYy [get_cells bufg_instance_name]

 

 

Thanks,
Deepika.
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Explorer
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Registered: ‎02-24-2016

Re: Sub-optimal placement for a BUFG-BUFG cascade pair -> how to solve?

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As for BUFGCTRL_XxYy, is the XxYy location coordinates? How to know the XxYy?

 

How can I do the same via GUI?

 

Thank you

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎05-07-2015

Re: Sub-optimal placement for a BUFG-BUFG cascade pair -> how to solve?

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HI @dmitry1417

 

Open synthesized design, In the netlist tab, select the BUGMUX  primitve and drag it on the device view , place it some BUFG location at the center of the device.
Do the same  for the BUFGCE instance and place it on BUFG location adjacent to the BUFGMUX location. 
when you save , respective LOC constraints will  be written into the xdc file.

Thanks
Bharath
--------------------------------------------------​--------------------------------------------
Please mark the Answer as "Accept as solution" if information provided addresses your query/concern.
Give Kudos to a post which you think is helpful.
--------------------------------------------------​-------------------------------------------

View solution in original post

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Moderator
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Registered: ‎01-16-2013

Re: Sub-optimal placement for a BUFG-BUFG cascade pair -> how to solve?

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@dmitry1417,

 

In Vivado GUI, You can use the drag and drop option which will easily place/loc the instance at desired location. 

Please check page number 67 in below user guide which gives details on drag and drop of instances:

http://www.xilinx.com/support/documentation/sw_manuals/xilinx2012_2/ug893-vivado-ide.pdf

 

Once you save the design then the changes will be captured in constraint file.

 

--Syed

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Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
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Registered: ‎02-24-2016

Re: Sub-optimal placement for a BUFG-BUFG cascade pair -> how to solve?

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Thanks!

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Re: Sub-optimal placement for a BUFG-BUFG cascade pair -> how to solve?

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@dmitry1417,

 

If the issue is resolved  then please close this thread by marking the post which helped as "Accept as Solution"

 

--Syed

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Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
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Re: Sub-optimal placement for a BUFG-BUFG cascade pair -> how to solve?

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Solved :-)

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Explorer
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Registered: ‎08-12-2019

Re: Sub-optimal placement for a BUFG-BUFG cascade pair -> how to solve?

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你好,我使用的是virtex ultraScale+,我也遇到了这样的问题,请问:
In the netlist tab, select the BUGMUX primitve and drag it on the device view , place it some BUFG location at the center of the device
没搞懂这是什么意思,能解释清楚一点么?谢谢
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