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fpgalearner
Voyager
Voyager
1,023 Views
Registered: ‎04-11-2016

Submodule not get instantiated

Hi,

I have a design in vu440. A top Module and several submodules. One submodule have problem. It is inside generate statement with 32 of the same submodule.

When I take only one of the this submodule, its gets instantiated inside top module and also works as expected but when I instantiate all 32 of submodule within generate statement, it doesn’t get instantiated and oviously design doesn’t work.

But it works in vcs simulation.

Vivado doesn’t report any error during implementation and timing is also clean.

What could be the reason?

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17 Replies
rshekhaw
Xilinx Employee
Xilinx Employee
1,021 Views
Registered: ‎05-22-2018

Hi @fpgalearner ,

I guess the particular sub modules are getting trimmed out.

If that is the scenario,  please run synthesis with -verbose and in log we can have info or warning on why the particular modules are getting trimmed out.

Thanks,

Raj

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fpgalearner
Voyager
Voyager
959 Views
Registered: ‎04-11-2016

@rshekhaw 

with -verbose option I got several of these:

INFO: [Opt 31-315] Cell of type LUT6 is reduced to LUT4, due to redundant pins:
INFO: [Opt 31-47] Cell absorbed into downstream logic: LUT1 cell genblk4[4].I_0_
INFO: [Opt 31-131] Removed net:

and don't know why?

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marcb
Moderator
Moderator
928 Views
Registered: ‎05-08-2012

Hi @fpgalearner 

The "redundant pins" would imply that the source is the same. This should be viewable from the elaborated design. Is this the case? Adding a KEEP or DONT_TOUCH might resolve the issue.

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fpgalearner
Voyager
Voyager
871 Views
Registered: ‎04-11-2016

@marcb @rshekhaw 

By using only opt_design -retarget option instead of default opt_design the trimming doesn't happen but the design doesn't work. I think this is because of big timing violation. which I am fixing now in place and route design by adding directives instead of default as:

 place_design  -directive AltSpreadLogic_high
route_design  -directive AlternateCLBRouting

 

But it took 23 hours to build. Yes you read right 23 hours. I don't know if it is normal for big design?

 

and the resource consumption of the design in vu440 is very high:

1. CLB Logic
------------

+----------------------------+---------+-------+-----------+-------+
|          Site Type         |   Used  | Fixed | Available | Util% |
+----------------------------+---------+-------+-----------+-------+
| CLB LUTs                   | 2185697 |     0 |   2532960 | 86.29 |
|   LUT as Logic             | 2185316 |     0 |   2532960 | 86.28 |
|   LUT as Memory            |     381 |     0 |    459360 |  0.08 |
|     LUT as Distributed RAM |     336 |     0 |           |       |
|     LUT as Shift Register  |      45 |     0 |           |       |
| CLB Registers              | 1486679 |     0 |   5065920 | 29.35 |
|   Register as Flip Flop    | 1481303 |     0 |   5065920 | 29.24 |
|   Register as Latch        |    5376 |     0 |   5065920 |  0.11 |
| CARRY8                     |    6248 |     0 |    316620 |  1.97 |
| F7 Muxes                   |     125 |     0 |   1266480 | <0.01 |
| F8 Muxes                   |       3 |     0 |    633240 | <0.01 |
| F9 Muxes                   |       0 |     0 |    316620 |  0.00 |
+----------------------------+---------+-------+-----------+-------+

 

If opt_design is completely removed and take only synth, place and route, does it have any impact on overall design? better to say generated bitfile?

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rshekhaw
Xilinx Employee
Xilinx Employee
838 Views
Registered: ‎05-22-2018

Hi @fpgalearner ,

Opt_design is mandatory phase, it should not be skipped:

• opt_design
• power_opt_design (optional)
• place_design
• phys_opt_design (optional)
• route_design
• phys_opt_design (optional)
• write_bitstream

Regarding large runtime please check below AR#:

https://www.xilinx.com/support/answers/71571.html

Thanks,

Raj

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fpgalearner
Voyager
Voyager
810 Views
Registered: ‎04-11-2016

@rshekhaw 

The opt_design command performs the following optimizations by default:

   *  Retarget

   *  Constant Propagation

   *  Sweep

   *  Global Buffer (BUFG) optimizations

   *  DSP Register optimizations

   *  Shift-Register Logic optimizations

   *  Block RAM Power optimizations

   *  Implement MIG cores

   *  Implement Debug cores

 

but taking only one option like opt_design -retarget is OK?

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rshekhaw
Xilinx Employee
Xilinx Employee
797 Views
Registered: ‎05-22-2018

Hi @fpgalearner .

In that sense, yes you can until and unless your design is functioning correctly.

Thanks,

Raj

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fpgalearner
Voyager
Voyager
686 Views
Registered: ‎04-11-2016

@rshekhaw @marcb 

I synthesized separately the submodule having more logics with -mode out_of_context in Vivado GUI, synthesis doesn't report any error but the resource utilization graph shows 138 % LUT. See attachment.

But when I try to open synthesized design, It takes about 1 hour to open and after that vivado crash. Therefore I can't check resource_utilization command.

Does it mean this design can not be implemented in this vu440 device and need even bigger FPGA?

or I am doing something wrong?

 

 

lut_vivado.JPG
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marcb
Moderator
Moderator
662 Views
Registered: ‎05-08-2012

Hi @fpgalearner.

The utilization can be checked with the post-synthesis design. I would suggest doing so by opening the synthesized design, and entering report_utilization. This should be lower after opt_design. 

Since you are only using the opt_design -retarget argument, the other default stages are not preformed. The -sweep & -propconst arguments will remove much of the unnecessary logic, which might allow the utilization to fit the architecture 

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fpgalearner
Voyager
Voyager
643 Views
Registered: ‎04-11-2016

@marcb concerning "The utilization can be checked with the post-synthesis design. I would suggest doing so by opening the synthesized design, and entering report_utilization. This should be lower after opt_design."

It can not be opened. It took 1 hr then Vivado crashes.

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marcb
Moderator
Moderator
593 Views
Registered: ‎05-08-2012

Hi @fpgalearner 

A couple things to try would be:

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fpgalearner
Voyager
Voyager
532 Views
Registered: ‎04-11-2016

@marcb @rshekhaw 

using (* DONT_TOUCH = “yes” *) like this has solved trimming problem:


 generate
         for (genvar i=0; i<ds; i=i+1) begin

(* DONT_TOUCH = “yes” *) example_dt_ver U0

(.clk(clk),

.in1(a),

.in2(b),

out1(c));

         end

   endgenerate

and consumes only 18 % resources but design doesn't work as expected.

Is (* DONT_TOUCH = “yes” *) goes above generate like?

(* DONT_TOUCH = “yes” *) 

generate
         for (genvar i=0; i<ds; i=i+1) begin

 example_dt_ver U0

(.clk(clk),

.in1(a),

.in2(b),

out1(c));

         end

   endgenerate

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calibra
Scholar
Scholar
526 Views
Registered: ‎06-20-2012

@fpgalearner 

Have you try to compile the submodule out_of_context and instantiate it as an IP.

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fpgalearner
Voyager
Voyager
523 Views
Registered: ‎04-11-2016

@calibra 

yes, in that case I got bitwidth of a port mismatch error. 

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calibra
Scholar
Scholar
516 Views
Registered: ‎06-20-2012

@fpgalearner 

"yes, in that case I got bitwidth of a port mismatch error. "

Do you know why ?

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fpgalearner
Voyager
Voyager
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Registered: ‎04-11-2016

@calibra 

well, 2 bits of a vector port is provided constant value.

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calibra
Scholar
Scholar
495 Views
Registered: ‎06-20-2012

@fpgalearner 

Sorry but i don't understand.

You got a port mismatch bitwidth  error.

So the out_of_order compiler remove 2 output port bits ?

 

 

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