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Visitor volta
Visitor
1,748 Views
Registered: ‎08-05-2016

Synchronous and asynchronous Flip-Flop

Hi,

 

During the implementation I see that each SLICE contains eight flip-flops (FF_INIT), and when I study the Libraries Guide, I can see a lot of different registers/latches instances.

 

For example, FDCE is a Flip-Flop with asynchronous clear, while FDRE is Flip-Flop with synchronous reset. I have done some test in order to learn how they can be implemented, and after the place and route I discovered they can be placed in the same SLICE and in the same FF_INIT.

 

This result a little confusing to me, how the tools can create a synchronous or an asynchronous reset using the same physical FF_INIT?

 

Thanks

 

Volta

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Historian
Historian
1,734 Views
Registered: ‎01-23-2009

Re: Synchronous and asynchronous Flip-Flop

That is the power of Field Programmable Gate Arrays.

 

Each of the eight flip-flops within the slice have the circuitry required for a superset of the required flip-flop (and latch)  functions. The physical flip-flops in the slice each have the transistors (and hence the capability) of performing

  - Flip-flop with synchronous set/reset

  - Flip-flop with asynchronous preset/clear

  - Latch with (a variety of synchronous/asynchronous preset/clear stuff - I don't use latches)

 

Like all the other things in the FPGA, the tools decide how to configure each element, which determines which personality (of the available personalities) the element will use for this design.

 

The same thing happens for lots of other things in the FPGA

  - The LUT

     - one LUT6 (or smaller)

     - two LUT5 sharing inputs (or smaller)

     - a 64x1 single ported RAM (or 1/2 of a dual ported RAM) - SLICEM only

     - a 32x1 Shift Register - SLICEM only

  - The ILOGIC/OLOGIC

      - SDR flip-flop

      - DDR flip-flop

      - ISERDES/OSERDES

  - The BRAM

      - 2x18kB dual port SRAM

      - 1x36kB dual port SRAM

      - 1x36kB FIFO

      - 1x18kb SRAM + 1x18kb FIFO

      - different widths (x1, x2, x4, x8, x9, x16, x18, x32, x36, x64 (in some configurations), x72 (in some configurations)

      - different write modes

      - 1 or 2 clock read latency

      - synchronous or asynchronous ports

 

(etc...)

 

Avrum

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Visitor volta
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1,696 Views
Registered: ‎08-05-2016

Re: Synchronous and asynchronous Flip-Flop

Well, I am working in my first important project with FPGAs at the moment and I have to admit I am impressed, it is sure there are a lot of design and hard work and FPGAs are really an artwork.

 

I want to learn more about it, is there any documentation that explains how the physical Flip-Flips use the transistors to get the capability of switching between the synchronous and asynchronous reset?

 

Thank you very much.

 

Volta

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Historian
Historian
1,692 Views
Registered: ‎01-23-2009

Re: Synchronous and asynchronous Flip-Flop

 is there any documentation that explains how the physical Flip-Flips use the transistors to get the capability of switching between the synchronous and asynchronous reset?

 

Not that I know of. Many Xilinx circuits are patented, so you could try and search through the patent database... (maybe @austin can point you in the right direction).

 

But it isn't that hard to envision - the design of synchronous and asynchronous FFs are well known, merging  them together to form a super-set with control signals determining the current behavior doesn't seem like a wildly complicated task (not that I am trying to minimize the accomplishments of Xilinx!).

 

However, the fact that they do work (and work as expected) is really what is most important for us users!

 

Avrum

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