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Visitor ckteng
Visitor
497 Views
Registered: ‎06-22-2019

Synthesis removing required IBUFs

Hello, my problem is that IBUFs in my code are being removed during synthesis. This causes an Implentation error stating I require IBUFs to drive my IBUFDS_GTE2 cell. The problem is related to this post except I already have IBUFs and can't get them to stay: https://forums.xilinx.com/t5/Implementation/Vivado-IBUFDS-GTE2-driven-by-IBUF/td-p/383187

Here's the code:

IBUF refclk_p_buf
(.I(refclk_pad_p),
.O(refclk_p_buffed));

IBUF refclk_n_buf
(.I(refclk_pad_n),
.O(refclk_n_buffed));

IBUFDS_GTE2 ibufds_refclk0
(
.O (refclk_i),
.ODIV2 (),
.CEB (tied_to_ground_i),
.I (refclk_p_buffed),
.IB (refclk_n_buffed)
);

Is there a property I can set in the constraints file or some setting to prevent the IBUFs from being removed?

Thanks!

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12 Replies
Visitor ckteng
Visitor
475 Views
Registered: ‎06-22-2019

Re: Synthesis removing required IBUFs

I tried using the DONT_TOUCH property and the IBUFs still disappear.

0 Kudos
461 Views
Registered: ‎09-17-2018

Re: Synthesis removing required IBUFs

The gigabit transceivers never use IBUF -

The receive input pins are dedicated (no need for anything more).

Not sure why you think you need IBUF, as those are only used for regular IO pins as inputs.

l.e.o.

Visitor ckteng
Visitor
437 Views
Registered: ‎06-22-2019

Re: Synthesis removing required IBUFs

Thanks for your reply! During the implementation phase complains of a DRC error if they aren't there. The IP has them in the code.

Based on what you're saying, perhaps the differential clocks need to come from the FPGA pins and not from an internal clock wizard. Does that seem right? It's JESD204B IP.

 

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Xilinx Employee
Xilinx Employee
404 Views
Registered: ‎05-22-2018

Re: Synthesis removing required IBUFs

Hi @ckteng ,

Are you trying to synthesize your design in OOC mode?

If yes then try to synthesis by setting it to Global.

Thanks,

Raj

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Visitor ckteng
Visitor
396 Views
Registered: ‎06-22-2019

Re: Synthesis removing required IBUFs

Thanks I think I tried that but it didn't change things. Are IBUFs only for module inputs or FPGA top-level inputs?

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Xilinx Employee
Xilinx Employee
395 Views
Registered: ‎05-14-2008

Re: Synthesis removing required IBUFs

Which Vivado version are you using?

Is the code snippet from Xilinx IP?

The IBUFDS_GTE2 is the dedicated differential input buffer that is used by the GT dedicated reference clock input. It does not need IBUFs before it. The I and IB pins should be connected to the top level port directly.

One possible cause to the error is that you did not map this differential clock input to the GT dedicated ref clock ports.

-vivian

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Xilinx Employee
Xilinx Employee
390 Views
Registered: ‎05-14-2008

Re: Synthesis removing required IBUFs


@ckteng wrote:

Based on what you're saying, perhaps the differential clocks need to come from the FPGA pins and not from an internal clock wizard. Does that seem right? It's JESD204B IP.

 


What do you mean by "internal clock wizard"? Does the differential clock come from MMCM in your design? Yes, it needs to come from the dedicated FPGA pins for GT.

-vivian

-------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------------------------------
如果提供的信息能解决您的问题,请标记为“接受为解决方案”。
如果您认为帖子有帮助,请点击“奖励”。谢谢!
-------------------------------------------------------------------------------------------------
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Visitor ckteng
Visitor
381 Views
Registered: ‎06-22-2019

Re: Synthesis removing required IBUFs

Hi Vivian, yes it is Xilinx IP and the IBUFs in the code were already there.

I used a clock wizard to generate the clocks that go to the IBUFs.

It sounds like you are saying the IP clks should be directly connected to specific FPGA GT clock ports.

How do I make sure the ports are mapped to specific FPGA pins? A constraint command?
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Visitor ckteng
Visitor
381 Views
Registered: ‎06-22-2019

Re: Synthesis removing required IBUFs

Hi Vivian, yes the diff clks come from the MMCM. OK, I guess I need to send the diff clocks directly from the FPGA GT pins. I'll look it up but if you know how please post here so the solution is published. Thanks!
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Xilinx Employee
Xilinx Employee
337 Views
Registered: ‎05-14-2008

Re: Synthesis removing required IBUFs

Check the Transceiver User Guide of the device that you're using for the GT usage.

For example, for 7-series GTX/GTH it is UG476.

And check the package files of the device family for which ports are the dedicated pins.

The GT reference clock has to be coming from the dedicated FPGA pins.

Usually if you're using the Xilinx IP that contains GTs, the IP will provide the necessary constraints to map the GT and its ports to the dedicated sites. 

It is probably due to the incorrect usage of the GT reference clock connected to MMCM, so the location constraints do not work.

Make sure you have the ports connected correctly and see if it works.

-vivian

-------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------------------------------
如果提供的信息能解决您的问题,请标记为“接受为解决方案”。
如果您认为帖子有帮助,请点击“奖励”。谢谢!
-------------------------------------------------------------------------------------------------
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Visitor ckteng
Visitor
306 Views
Registered: ‎06-22-2019

Re: Synthesis removing required IBUFs

Very helpful, thanks!!!

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297 Views
Registered: ‎07-23-2019

Re: Synthesis removing required IBUFs


@ckteng wrote:

Thanks I think I tried that but it didn't change things. Are IBUFs only for module inputs or FPGA top-level inputs?


IBUF, OBUF, etc. are only for the top level file i/os connecting to physical pins

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