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Adventurer
Adventurer
411 Views
Registered: ‎10-29-2017

Tandem PCIe with field updates in zynq XCZU19EG

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Hi, 

   I'm working with zynq device XCZU19EG enabling 'Tandem PCIe with field updates'. I have many user I/O in the design assigned in bank 65,which are not related to PCIe. With reference to PG213, page no. 113, by using OBUFTDS, I tried to declare those pins as output pins in bank 65. But I'm getting placement failed saying the following error.

image.png

Is it possible to use user I/O pins with OBUFT in bank 65 or my declaration is wrong?

Please help on this. 

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Xilinx Employee
Xilinx Employee
349 Views
Registered: ‎05-08-2012

Re: Tandem PCIe with field updates in zynq XCZU19EG

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Hi @sumaiya

The PERSIST constraint looks to be set here. Looking at the below AR, this is not needed for Tandem PCIe.

https://www.xilinx.com/support/answers/56453.html


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Xilinx Employee
Xilinx Employee
388 Views
Registered: ‎05-08-2012

Re: Tandem PCIe with field updates in zynq XCZU19EG

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Hi @sumaiya 

The image did not successfully attach. Can you add the text of the error? 


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Adventurer
Adventurer
363 Views
Registered: ‎10-29-2017

Re: Tandem PCIe with field updates in zynq XCZU19EG

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Hi @marcb,

     The error is as follows: 

[DRC HDTC-10] Config banks not available to second stage I/O: For Tandem PROM flow, second stage I/O 'OBUFTDS_inst_1' can not use configuration bank '65'.

[DRC HDTC-10] Config banks not available to second stage I/O: For Tandem PROM flow, second stage I/O 'OBUFTDS_inst_2' can not use configuration bank '65'.

[DRC HDTC-10] Config banks not available to second stage I/O: For Tandem PROM flow, second stage I/O 'mpsoc_bd_pin_check_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST' can not use configuration bank '65'.

[DRC HDTC-10] Config banks not available to second stage I/O: For Tandem PROM flow, second stage I/O 'mpsoc_bd_pin_check_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST' can not use configuration bank '65'.

  • [Vivado_Tcl 4-23] Error(s) found during DRC. Placer not run.





 

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Xilinx Employee
Xilinx Employee
350 Views
Registered: ‎05-08-2012

Re: Tandem PCIe with field updates in zynq XCZU19EG

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Hi @sumaiya

The PERSIST constraint looks to be set here. Looking at the below AR, this is not needed for Tandem PCIe.

https://www.xilinx.com/support/answers/56453.html


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Adventurer
Adventurer
323 Views
Registered: ‎10-29-2017

Re: Tandem PCIe with field updates in zynq XCZU19EG

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Hi @marcb,

      I'm doing project in Project flow mode. After setting PERSIST to false, I can able to generate bitstream. Earlier bitstream was generated without any errors. After enabling 'Tandem PCIe with field updates' in PCIe block of the design (Note: 'Tandem PCIe with field updates' can be worked only in non-project flow mode), I'm getting

ERROR: [Place 30-681] Sub-optimal placement for a global clock-capable IO pin and MMCM pair. As a workaround for this error, please insert a BUFG in between the IO and the MMCM.

After inserting buffer, 

ERROR: [place 30-675] set_property clock_dedicated_route false get_nets clk is occuring. 

But the above procedure is not advisable as shown in the tool. So, my question

1. Is enabling 'Tandem PCIe with field updates' in project-flow mode is wrong? 

2. Is it a standard way to complete the design by following the above procedures which are not advisable? Will my execution affect because of this? 

3. Input clock is already located in GC pin. Do I need to re-locate the clock to other GC Pin as it creates placement error with the current pin?  

 

Please guide me through this.

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Xilinx Employee
Xilinx Employee
302 Views
Registered: ‎05-08-2012

Re: Tandem PCIe with field updates in zynq XCZU19EG

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Hi @sumaiya 

 

Could you list the entire message, or maybe post the log? There is a section below what you showed which contains the relavant cells and physical sites. This information is crucial for resolving these errors.

 


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Adventurer
Adventurer
296 Views
Registered: ‎10-29-2017

Re: Tandem PCIe with field updates in zynq XCZU19EG

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Hi @marcb,

What log do you require?

How will I get it? 

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Xilinx Employee
Xilinx Employee
239 Views
Registered: ‎05-08-2012

Re: Tandem PCIe with field updates in zynq XCZU19EG

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Hi @sumaiya 

The log file would contain the error you are concerned with:

ERROR: [place 30-675] set_property clock_dedicated_route false get_nets clk is occuring.

For project mode designs, this would be in the <project_name>/.runs/<impl_run>/runme.log file, and normally for non-project mode designs, the vivado.log would contain this. It could be in a separte file if you have scripted the flow in such a way as to generate multiple log files. 


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Adventurer
Adventurer
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Registered: ‎10-29-2017

Re: Tandem PCIe with field updates in zynq XCZU19EG

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Hi @marcb

     Thanks for your reply.

     Clock issue has been resolved. 

      Can you please help me with the following queries?

1. I'm able to generate two Bitstreams (stage 1 & stage 2) by enabling 'TANDEM PCIE WITH FIELD UPDATES' using xdma IP in project flow mode. In xilinx demo video, it has been mentioned that 'TANDEM PCIE WITH FIELD UPDATES' doesn't support project flow mode. Is my procedure wrong while generating Bitstream for tandem pcie with field updates in project flow mode? Will it work if I proceed further? Or we can work on 'TANDEM PCIE WITH FIELD UPDATES' only in non-project flow mode? 

Can you please help me which is the best way to implement 'TANDEM PCIE WITH FIELD UPDATES'?  

Xilinx demo video link for 'TANDEM PCIE WITH FIELD UPDATES' 

https://youtu.be/KZI8aogXcCA

 

This video walks through the process of creating a PCI Express solution that uses the Tandem with Field Updates flow when using the AXI Bridge for PCI Express Gen3 Subsystem. The Tandem part of the flow allows for the PCIe block to be visible in less than 100ms and the Field Update means designs ...
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Xilinx Employee
Xilinx Employee
193 Views
Registered: ‎05-08-2012

Re: Tandem PCIe with field updates in zynq XCZU19EG

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Hi @sumaiya 

Please start a new post. New posts should be started for every separate topic discussed. This is going on the third different topic.

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Adventurer
Adventurer
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Registered: ‎10-29-2017

Re: Tandem PCIe with field updates in zynq XCZU19EG

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Okay, Thanks for the response.

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