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Observer
Observer
251 Views
Registered: ‎09-27-2019

The implementation of the FPGA Validation

Hi all,

Recently, I compile a complex project, but the project cannot meet the timing require. during the implementation, the vivado shows design has a large number of hold violators. This is likely a design or constraint issue. Router is turning off hold fixing.
Resolution: You can turn off flag route.enableHoldExpnBailout to disable hold expansion based bailout to continue fixing hold.

but the RTL code has been simulated and it's success

How Can I do ???

TU1.JPGtu2.JPG

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Moderator
Moderator
240 Views
Registered: ‎11-04-2010

For WHS, -4.7ns is too large for tool to fix it directly.

Please check the timing report and fix the hold time violation by correcting the xdc or using the appropriate clock structure.

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Observer
Observer
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Registered: ‎09-27-2019

what's the MAX value that the tool can fix the hold time directly and easily?

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Highlighted
83 Views
Registered: ‎06-21-2017

If the violations at this stage are more than 0.1 or 0.2 nS, you need to fix the problem in the design.  You may have a bad clock structure, such  as non-clock primitives in the clock tree or using a non-clock capable pin as a clock input.  There may be improper or unconstrained clock domain crossings.  You need to look at the failing paths and fix the basic issues.

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Observer
Observer
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Registered: ‎09-27-2019

 
 

clock.JPG

 

Hi 

This is my design clock tree, there are many gate clock. and I have use the vivado gated_clock_conversion to concert the gate clock.

there is a large WHS, 4ns.

As we know, the clock1 is  a global clock, and how I can optimize the clock, so that the clock can be timing closure.

 

clock.JPG
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