09-15-2020 11:58 PM
I'm trying to write a program for XC6VLX240T with ISE 12.4
My code is below:
entity XC6VLX240T is
Port ( CTRL1 : in STD_LOGIC;
CLK : in STD_LOGIC;
Bank_12: inout std_logic_vector(6 downto 1)
architecture Behavioral of XC6VLX240T is
if (CTRL1 = '0') and (CLK'event and CLK = '1') then
Bank_12 <= (others => '0');
if (CTRL1 = '1') and (CLK'event and CLK = '1') then
Bank_12 <= (others => '1');
After Design Implementation I recieve warnings:
WARNING:Par:288 - The signal CLK_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal CTRL1_IBUF has no load. PAR will not attempt to route this signal.
FPGA pins (bank12) are in a HIGH state in spite of CLK and CTRL1 states
If I don't use CLK, everything is good: no warnings and FPGA works as I expect.
Is there any assumptions what am I doing wrong?