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Registered: ‎11-01-2019

The input signal without load

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I'm trying to write a program for XC6VLX240T with ISE 12.4

My code is below:

 

entity XC6VLX240T is

Port ( CTRL1 : in STD_LOGIC;
          CLK : in STD_LOGIC;

          Bank_12: inout std_logic_vector(6 downto 1)

);

end entity;

architecture Behavioral of XC6VLX240T is

begin

process(CTRL1, CLK)
   begin

-- Uol
      if (CTRL1 = '0') and (CLK'event and CLK = '1') then
         Bank_12 <= (others => '0');
      end if;

-- Uoh
      if (CTRL1 = '1') and (CLK'event and CLK = '1') then
         Bank_12 <= (others => '1');
      end if;

   end process;

end Behavioral;

 

After Design Implementation  I recieve warnings:

WARNING:Par:288 - The signal CLK_IBUF has no load. PAR will not attempt to route this signal.

WARNING:Par:288 - The signal CTRL1_IBUF has no load. PAR will not attempt to route this signal.

 

FPGA pins (bank12) are in a HIGH state in spite of CLK and CTRL1 states

 

If I don't use CLK, everything is good: no warnings and FPGA works as I expect.

 

Is there any assumptions what am I doing wrong?

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67 Views
Registered: ‎11-01-2019

Found the answer here: https://www.xilinx.com/support/answers/14047.html 

Need to describe the processes the other way

 

View solution in original post

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1 Reply
Highlighted
68 Views
Registered: ‎11-01-2019

Found the answer here: https://www.xilinx.com/support/answers/14047.html 

Need to describe the processes the other way

 

View solution in original post

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