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3,972 Views
Registered: ‎07-05-2010

The logic does not fit onto the chip in this form

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while implementing my toplevel design i got following error during MAP phase:

 

ERROR:Place:673 - DSP component
   "hsdac_controller/gmsktransmitter_3aug11_2009a_cw/gmsktransmitter_3aug11_2009a_x0/gmsk_if_modulator_f95ae2c8a8/gmsk_modulator_passband2_c08e1bee03/xilinx_fir_c32fb8c465/fir_compiler_5_0/fr_cmplr_v5_0_0fc8b18baf341060_instance/blk00000003/blk000000a7" is the start of a cascade of DSP components. They need to
   be placed in correct order into vertically adjacent DSP sites. An issues has
   been detected with the correct placement of these DSP components.
   The reason for this issue:
   The logic does not fit onto the chip in this form.The following components
   are part of this structure:
ERROR:Pack:1654 - The timing-driven placement phase encountered an error.

 

my verilog toplevel has three different submodules as components : one is xps project and other two are system generator models.... i am using ise 12.1 + matlab r2009a..my target device is xc5vfx100t.

thanks

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Highlighted
4,746 Views
Registered: ‎07-05-2010

error message suugests the problem in fir compilerv5.0..

in the 'detailed implemenatation' tab   we have a option as 'data buffer type' earlier i set it as 'block' from drop down menu, now when i set it as ' automatic' then the issue is resolved.

 

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Scholar
Scholar
3,959 Views
Registered: ‎07-01-2008

The xc5vfx100t device has a DSP column 64 sites tall. The error message suggests that you have a cascaded DSP chain that is taller than that. I suggest that you target a larger part as an experiment  so that you can examine the cascaded DSPs in FPGA Editor and see if there is really a chain that large.

Highlighted
4,747 Views
Registered: ‎07-05-2010

error message suugests the problem in fir compilerv5.0..

in the 'detailed implemenatation' tab   we have a option as 'data buffer type' earlier i set it as 'block' from drop down menu, now when i set it as ' automatic' then the issue is resolved.

 

View solution in original post

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