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Visitor
Visitor
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Registered: ‎11-29-2017

The signal is incomplete (ISE 14.7, XST)

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Hello everyone,

 

I am constantly getting this warning "The signal is incomplete. The signal does not drive any load pins in the design.".

 

However, this warning occurs on "Generate Programming File", whereas "Synthesis - XST" and "Implement Design" finish without any warnings.

 

If I understand this correctly, this warning tells me that the signal is not connected to a load. However, I've checked the generated RTL schematic, and it is clear that the signal is connected to a logic block.

 

Question is - how can I get rid of this annoying warning?

 

Please find attached the full (compiled) project.

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Visitor
Visitor
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Registered: ‎11-29-2017

While analyzing the program, I've noticed that one part of the logic didn't exactly work as it was supposed to. This was caused by a range in one of the signals, and it was the main cause of the annoying warnings. The signal in question was used as an index of a byte array (memory), and this was causing that part of the array was never used. Unfortunately, XST does not give detailed explanations of generated warnings, or I don't know how to read them.

 

Once I've fixed this range issue, everything works just fine, without any warnings.

 

To conclude, never neglect warnings!

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-01-2008
XST trim the signals which are not connected to produce output . you can ignore the warning, The cause is that I let some output ports unconnected. The reason is XST to trim the unconnected ports, along with several other logic driving the output. Therefore, I output the unused output to some dummy ports.

If all signals are completely routed at PAR, this warning can be safely ignored.
Thanks and Regards
Balkrishan
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Visitor
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Registered: ‎11-29-2017

I would still like to get rid of warnings, if possible.

 

As I can see it, PAR finishes without warnings. Does this mean that all signals are connected?

 

Here is a detailed warning generated in "Generate Programming File" phase:

 

WARNING:PhysDesignRules:367 - The signal
<protocol_0_ram_din<6>/ram_interface_0/ram_0/Mram_ram7/A> is incomplete. The
signal does not drive any load pins in the design.

 

I even tried to connect protocol_0_ram_din signal to an unused port, but I still get the same warning.

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Moderator
Moderator
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Registered: ‎01-16-2013

@mali_zeus,

 

Yes, If there are any unrouted nets during PAR then you will see the warning. You can also check *.unroutes file in ISE project directory which will contain unrouted nets. If all the nets are routed then you will see "All signals are completely routed" in .unroutes file. 

 

If all the nets are completely routed, you can ignore this warning.

 

--Syed

 

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Did you check our new quick reference timing closure guide (UG1292)?
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Xilinx Employee
Xilinx Employee
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Registered: ‎08-01-2008
Sometime Its not possible get ride of all the warnings . The reason is FPGA are programmable device and if you are using Xilinx which can configure n number of ways . In such scenario it always possible to get such type of warning . Tools just informing you so you should know how the tool handled your logic. All the unused port trim at generate bitstream stage so you can safely ignore these warnings .
Thanks and Regards
Balkrishan
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Visitor
Visitor
3,539 Views
Registered: ‎11-29-2017

While analyzing the program, I've noticed that one part of the logic didn't exactly work as it was supposed to. This was caused by a range in one of the signals, and it was the main cause of the annoying warnings. The signal in question was used as an index of a byte array (memory), and this was causing that part of the array was never used. Unfortunately, XST does not give detailed explanations of generated warnings, or I don't know how to read them.

 

Once I've fixed this range issue, everything works just fine, without any warnings.

 

To conclude, never neglect warnings!

View solution in original post

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Highlighted
Moderator
Moderator
2,371 Views
Registered: ‎01-16-2013

@mali_zeus,

 

Yes, always keep a watch on warnings :-) 

 

As the issue is resolved, please close this thread by marking the post as "Accept as Solution"

 

--Syed

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Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------
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