Translate failed

[sandeshnj]

Version used:10.1 ISE

Any change in the code is getting synthsized, but failing to translate giving the error: "all the net names in the UCF are not existing". The number of errors are equal to the number of nets declared in UCF.

[siktap]

Yes. While synthesizing, the net names might have changed. You have relook at the net name.

Open technology schematic after XST. In the schematic, click a net or instance.

•  Select View > Add Name to attach the name to the cursor.
•  Click in the schematic to place the name.

Sometimes using wildcharacters might help as well.

[vijayak]

Hi,
Please attach the exact error given by the tool.

[driesd]

Hi Sandeshnj@sandeshnj,

alternatively to Sikta's suggestion:

---

@siktap wrote:

Yes. While synthesizing, the net names might have changed. You have relook at the net name.

Open technology schematic after XST. In the schematic, click a net or instance.

•  Select View > Add Name to attach the name to the cursor.
•  Click in the schematic to place the name.

Sometimes using wildcharacters might help as well.

---

I personally like to use PlanAhead. With PA you can also load the netlist and find the names of the nets/instances.

Best regards,

Dries

[gszakacs]

Some things to consider:

Net names in the UCF must match the top level port name in the design. 

For a Verilog project net names are case sensitive.

In some unusual cases you may have IO's instantiated in lower level modules.  In these cases the instance name will include the entire hierarchy, and the hierarchy separator (usually "/") can change with synthesis options.

Net names with subscripts are normally translated with < > instead of [ ] or ( ) as they were in the source code.

Synthesis options include "Add IO Buffers" (-iobuf) which is checked by default.  If you have un-checked this box, you will have no IO's after synthesis.

Errors in your logic can cause parts of a design or even the entire design to be removed.  "Trimmed" logic should be reported in the synthesis warnings.

[sandeshnj]

Thank u.

                 I am attaching the Translate Error report.

The code is having 169 nets. i am trying to route out some signals on to header to monitor on logic analyzer. the code was not getting updated to the changes made. so i tryed to clear project files. after doing this this error is getting populated.

[sandeshnj]

ERROR:ConstraintSystem:59 - Constraint <NET "adc_data_0" LOC = "AE24";>
   [dif_toplevel_nks3.ucf(8)]: NET "adc_data_0" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.
 
ERROR:ConstraintSystem:59 - Constraint <NET "adc_data_1" LOC = "AD25";>
   [dif_toplevel_nks3.ucf(9)]: NET "adc_data_1" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.
 
ERROR:ConstraintSystem:59 - Constraint <NET "adc_data_2" LOC = "AL32";>
   [dif_toplevel_nks3.ucf(10)]: NET "adc_data_2" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.
 
ERROR:ConstraintSystem:59 - Constraint <NET "adc_data_3" LOC = "AK32";>
   [dif_toplevel_nks3.ucf(11)]: NET "adc_data_3" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.
....................

Finally

 
NGDBUILD Design Results Summary:
  Number of errors:   165
  Number of warnings: 161
 
Total memory usage is 260632 kilobytes
 
 
One or more errors were found during NGDBUILD.  No NGD file will be written.
 
Writing NGDBUILD log file "ddc_dpc_50mhz_4pw_chg_2fs_cw.bld"...

[gszakacs]

So the question is, does your design have a top level scalar port named "adc_data_0" - or perhaps you have a top level vector port named "adc_data(3 downto 0)" (VHDL) or "adc_data[3:0]" (Verilog)?

For vector ports, as I mentioned above the net name will get translated by default to have < > around the subscript, however it is possible to change the default to [ ], ( ), or even _ .  Check the synthesis properties to see how it's set in your project and make sure that the syntax in the UCF file matches.

Another approach to this is to set the translate property "Allow unmatched LOC constraints" (-aul) to see if you can run through translate without errors.  Then if you run through to get a pad report you should find a lot uf unlocated items.  Check the syntax of the signal names for the unlocated items and you should be able to fix your UCF to match.

Alternately, you could use PlanAhead post-synthesis to see the names of the IO ports.

[siktap]

The error clearly indicates that these objects or names arent matching to your logical design. Hence please check in schematic or Planahead as earlier suggested. If these nets were present in your RTL and doesnt exist in the netlist , then these might have been trimmed off by synthesis.