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litebarb
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Registered: ‎02-03-2021

Tri Mode Ethernet Mac HDIO FMC Error

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Hi All,

I am currently using eval board Zynq UltraScale+ RFSoC ZCU1285, trying to implement a project with TEMAC IP Core. On the eval board there are two useable FMC slots, JA3 and JA4. I require both as I have two identical FMC (Low Pin Count) cards. Implementation and testing for TEMAC on JA3 works perfectly. After I modified the constraint file for the project to be suitable with JA4, I received critical warnings which led to Bit Stream errors. From what I understand, JA4 pins are connected to the HDIO FPGA bank while JA3 pins are connected to the HPIO FPGA bank. As I read further, according to this post here, HDIO bank doesn't seem to support IODELAY (automatically inserted by TEMAC Core), but I am not sure if that is the reason for the critical error I received. Could someone help me with this? Also, if this indeed is the cause for both the "rgmii_tx" and "rgmii_rx" errors, does this mean that TEMAC IP Core is not suitable to be used with JA4 FMC (HDIO Pins) slot? Any workaround for this?

Working constraints for JA3 (HP Pins):

 

 

 

set_property IOSTANDARD LVCMOS18 [get_ports {rgmii_txd[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii_txd[1]}]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii_txd[2]}]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii_txd[3]}]
set_property PACKAGE_PIN B28 [get_ports {rgmii_txd[0]}]
set_property PACKAGE_PIN E27 [get_ports {rgmii_txd[1]}]
set_property PACKAGE_PIN D27 [get_ports {rgmii_txd[2]}]
set_property PACKAGE_PIN C30 [get_ports {rgmii_txd[3]}]
set_property IOSTANDARD LVCMOS18 [get_ports rgmii_tx_ctl]
set_property IOSTANDARD LVCMOS18 [get_ports rgmii_txc]
set_property PACKAGE_PIN C31 [get_ports rgmii_tx_ctl]
set_property PACKAGE_PIN A28 [get_ports rgmii_txc]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii_rxd[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii_rxd[1]}]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii_rxd[2]}]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii_rxd[3]}]
set_property PACKAGE_PIN A29 [get_ports {rgmii_rxd[0]}]
set_property PACKAGE_PIN A30 [get_ports {rgmii_rxd[1]}]
set_property PACKAGE_PIN B32 [get_ports {rgmii_rxd[2]}]
set_property PACKAGE_PIN A32 [get_ports {rgmii_rxd[3]}]
set_property IOSTANDARD LVCMOS18 [get_ports rgmii_rx_ctl]
set_property IOSTANDARD LVCMOS18 [get_ports rgmii_rxc]
set_property PACKAGE_PIN G28 [get_ports rgmii_rx_ctl]
set_property PACKAGE_PIN G27 [get_ports rgmii_rxc]

 

 

 

 

NOT working constraints for JA4 (HDIO Pins):

 

 

 

set_property IOSTANDARD LVCMOS18 [get_ports {rgmii_txd[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii_txd[1]}]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii_txd[2]}]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii_txd[3]}]
set_property PACKAGE_PIN AR10 [get_ports {rgmii_txd[0]}]
set_property PACKAGE_PIN BA10 [get_ports {rgmii_txd[1]}]
set_property PACKAGE_PIN BB9 [get_ports {rgmii_txd[2]}]
set_property PACKAGE_PIN AY9 [get_ports {rgmii_txd[3]}]
set_property IOSTANDARD LVCMOS18 [get_ports rgmii_tx_ctl]
set_property IOSTANDARD LVCMOS18 [get_ports rgmii_txc]
set_property PACKAGE_PIN BA9 [get_ports rgmii_tx_ctl]
set_property PACKAGE_PIN AT10 [get_ports rgmii_txc]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii_rxd[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii_rxd[1]}]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii_rxd[2]}]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii_rxd[3]}]
set_property PACKAGE_PIN AP11 [get_ports {rgmii_rxd[0]}]
set_property PACKAGE_PIN AP10 [get_ports {rgmii_rxd[1]}]
set_property PACKAGE_PIN AP12 [get_ports {rgmii_rxd[2]}]
set_property PACKAGE_PIN AR11 [get_ports {rgmii_rxd[3]}]
set_property IOSTANDARD LVCMOS18 [get_ports rgmii_rx_ctl]
set_property IOSTANDARD LVCMOS18 [get_ports rgmii_rxc]
set_property PACKAGE_PIN AU11 [get_ports rgmii_rx_ctl]
set_property PACKAGE_PIN AU12 [get_ports rgmii_rxc]

 

 

 

 

Error messages:

Vivado 12-1411 Critical WarningCannot set LOC property of ports, Could not find a valid bel for the shape with the following elements:
trimac_fifo_block/tri_mode_ethernet_mac_i/U0/tri_mode_ethernet_mac_i/rgmii_interface/obuf_data[1].rgmii_txd_obuf_i
rgmii_txd[1]
trimac_fifo_block/tri_mode_ethernet_mac_i/U0/tri_mode_ethernet_mac_i/rgmii_interface/txdata_out_bus[1].rgmii_txd_out
trimac_fifo_block/tri_mode_ethernet_mac_i/U0/tri_mode_ethernet_mac_i/rgmii_interface/txdata_out_bus[1].delay_rgmii_txd

Vivado 12-1411Critical WarningCannot set LOC property of ports, Could not find a valid bel for the shape with the following elements:
trimac_fifo_block/tri_mode_ethernet_mac_i/U0/tri_mode_ethernet_mac_i/rgmii_interface/obuf_data[2].rgmii_txd_obuf_i
rgmii_txd[2]
trimac_fifo_block/tri_mode_ethernet_mac_i/U0/tri_mode_ethernet_mac_i/rgmii_interface/txdata_out_bus[2].rgmii_txd_out
trimac_fifo_block/tri_mode_ethernet_mac_i/U0/tri_mode_ethernet_mac_i/rgmii_interface/txdata_out_bus[2].delay_rgmii_txd

Vivado 12-1411Critical WarningCannot set LOC property of ports, Could not find a valid bel for the shape with the following elements:
trimac_fifo_block/tri_mode_ethernet_mac_i/U0/tri_mode_ethernet_mac_i/rgmii_interface/obuf_data[3].rgmii_txd_obuf_i
rgmii_txd[3]
trimac_fifo_block/tri_mode_ethernet_mac_i/U0/tri_mode_ethernet_mac_i/rgmii_interface/txdata_out_bus[3].rgmii_txd_out
trimac_fifo_block/tri_mode_ethernet_mac_i/U0/tri_mode_ethernet_mac_i/rgmii_interface/txdata_out_bus[3].delay_rgmii_txd

Vivado 12-1411Critical WarningCannot set LOC property of ports, Could not find a valid bel for the shape with the following elements:
trimac_fifo_block/tri_mode_ethernet_mac_i/U0/tri_mode_ethernet_mac_i/rgmii_interface/rgmii_tx_ctl_obuf_i
rgmii_tx_ctl
trimac_fifo_block/tri_mode_ethernet_mac_i/U0/tri_mode_ethernet_mac_i/rgmii_interface/rgmii_tx_ctl_out
trimac_fifo_block/tri_mode_ethernet_mac_i/U0/tri_mode_ethernet_mac_i/rgmii_interface/delay_rgmii_tx_ctl

Vivado 12-1411Critical WarningCannot set LOC property of ports, Could not find a valid bel for the shape with the following elements:
trimac_fifo_block/tri_mode_ethernet_mac_i/U0/tri_mode_ethernet_mac_i/rgmii_interface/rgmii_txc_obuf_i
rgmii_txc
trimac_fifo_block/tri_mode_ethernet_mac_i/U0/tri_mode_ethernet_mac_i/rgmii_interface/delay_rgmii_tx_clk_casc
trimac_fifo_block/tri_mode_ethernet_mac_i/U0/tri_mode_ethernet_mac_i/rgmii_interface/rgmii_txc_ddr
trimac_fifo_block/tri_mode_ethernet_mac_i/U0/tri_mode_ethernet_mac_i/rgmii_interface/delay_rgmii_tx_clk

Vivado 12-1411Critical WarningCannot set LOC property of ports, Illegal to place instance trimac_fifo_block/tri_mode_ethernet_mac_i/U0/tri_mode_ethernet_mac_i/rgmii_interface/rxdata_bus[0].delay_rgmii_rxd on site HDIOLOGIC_M_X0Y11. The location site type (HDIOLOGIC_M) and bel type (TFF_M) do not match the cell type (IDELAYE3). Instance trimac_fifo_block/tri_mode_ethernet_mac_i/U0/tri_mode_ethernet_mac_i/rgmii_interface/rxdata_bus[0].delay_rgmii_rxd belongs to a shape with reference instance trimac_fifo_block/tri_mode_ethernet_mac_i/U0/tri_mode_ethernet_mac_i/rgmii_interface/ibuf_data[0].rgmii_rxd_ibuf_i/INBUF_INST. Shape elements have relative placement respect to each other. The invalid location might results from a constraint on any of the instance in the shape.(details: presence of I/ODELAY or I/OSERDES is not supported in HDIO).
Vivado 12-1411Critical WarningCannot set LOC property of ports, Illegal to place instance trimac_fifo_block/tri_mode_ethernet_mac_i/U0/tri_mode_ethernet_mac_i/rgmii_interface/rxdata_bus[1].delay_rgmii_rxd on site HDIOLOGIC_S_X0Y11. The location site type (HDIOLOGIC_S) and bel type (TFF_S) do not match the cell type (IDELAYE3). Instance trimac_fifo_block/tri_mode_ethernet_mac_i/U0/tri_mode_ethernet_mac_i/rgmii_interface/rxdata_bus[1].delay_rgmii_rxd belongs to a shape with reference instance trimac_fifo_block/tri_mode_ethernet_mac_i/U0/tri_mode_ethernet_mac_i/rgmii_interface/ibuf_data[1].rgmii_rxd_ibuf_i/INBUF_INST. Shape elements have relative placement respect to each other. The invalid location might results from a constraint on any of the instance in the shape.(details: presence of I/ODELAY or I/OSERDES is not supported in HDIO).
Vivado 12-1411Critical WarningCannot set LOC property of ports, Illegal to place instance trimac_fifo_block/tri_mode_ethernet_mac_i/U0/tri_mode_ethernet_mac_i/rgmii_interface/rxdata_bus[2].delay_rgmii_rxd on site HDIOLOGIC_M_X0Y10. The location site type (HDIOLOGIC_M) and bel type (TFF_M) do not match the cell type (IDELAYE3). Instance trimac_fifo_block/tri_mode_ethernet_mac_i/U0/tri_mode_ethernet_mac_i/rgmii_interface/rxdata_bus[2].delay_rgmii_rxd belongs to a shape with reference instance trimac_fifo_block/tri_mode_ethernet_mac_i/U0/tri_mode_ethernet_mac_i/rgmii_interface/ibuf_data[2].rgmii_rxd_ibuf_i/INBUF_INST. Shape elements have relative placement respect to each other. The invalid location might results from a constraint on any of the instance in the shape.(details: presence of I/ODELAY or I/OSERDES is not supported in HDIO).
Vivado 12-1411Critical WarningCannot set LOC property of ports, Illegal to place instance trimac_fifo_block/tri_mode_ethernet_mac_i/U0/tri_mode_ethernet_mac_i/rgmii_interface/rxdata_bus[3].delay_rgmii_rxd on site HDIOLOGIC_S_X0Y10. The location site type (HDIOLOGIC_S) and bel type (TFF_S) do not match the cell type (IDELAYE3). Instance trimac_fifo_block/tri_mode_ethernet_mac_i/U0/tri_mode_ethernet_mac_i/rgmii_interface/rxdata_bus[3].delay_rgmii_rxd belongs to a shape with reference instance trimac_fifo_block/tri_mode_ethernet_mac_i/U0/tri_mode_ethernet_mac_i/rgmii_interface/ibuf_data[3].rgmii_rxd_ibuf_i/INBUF_INST. Shape elements have relative placement respect to each other. The invalid location might results from a constraint on any of the instance in the shape.(details: presence of I/ODELAY or I/OSERDES is not supported in HDIO).
Vivado 12-1411Critical WarningCannot set LOC property of ports, Illegal to place instance trimac_fifo_block/tri_mode_ethernet_mac_i/U0/tri_mode_ethernet_mac_i/rgmii_interface/delay_rgmii_rx_ctl on site HDIOLOGIC_S_X0Y7. The location site type (HDIOLOGIC_S) and bel type (TFF_S) do not match the cell type (IDELAYE3). Instance trimac_fifo_block/tri_mode_ethernet_mac_i/U0/tri_mode_ethernet_mac_i/rgmii_interface/delay_rgmii_rx_ctl belongs to a shape with reference instance trimac_fifo_block/tri_mode_ethernet_mac_i/U0/tri_mode_ethernet_mac_i/rgmii_interface/rgmii_rx_ctl_ibuf_i/INBUF_INST. Shape elements have relative placement respect to each other. The invalid location might results from a constraint on any of the instance in the shape.(details: presence of I/ODELAY or I/OSERDES is not supported in HDIO).
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1 Solution

Accepted Solutions
nanz
Moderator
Moderator
531 Views
Registered: ‎08-25-2009

Hi @litebarb ,

Yes, this is still the case that HDIO is not suitable for RGMII. This is due to RGMII spec and IO requirements. 


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If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs and our Versal Ethernet Sticky Note.

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3 Replies
litebarb
Visitor
Visitor
666 Views
Registered: ‎02-03-2021

I found a post here, where the moderator (@nanz) answers:

"The design needs I/ODELAY component for RGMII interface but generally the HD IO bank does not have these, so the HD IO pins cannot be LOCed for the RGMII interface pins.
Hence it is suggestible to LOC the RGMII interface IO pins with the HP or HR IO banks."

Can anyone verify that there is currently still no solution to LOC RGMII interface IO pins with HDIO pins? (Linked post was almost 3 years back)

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litebarb
Visitor
Visitor
597 Views
Registered: ‎02-03-2021

Hi, can any one help? Perhaps someone who is familiar with High Density (HD) IO pin features?

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nanz
Moderator
Moderator
532 Views
Registered: ‎08-25-2009

Hi @litebarb ,

Yes, this is still the case that HDIO is not suitable for RGMII. This is due to RGMII spec and IO requirements. 


-------------------------------------------------------------------------------------------

Don’t forget to reply, kudo, and accept as solution.

If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs and our Versal Ethernet Sticky Note.

-------------------------------------------------------------------------------------------

View solution in original post