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JPK17
Observer
Observer
370 Views
Registered: ‎03-11-2021

UART1 as EMIO causing error.

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Hi all,

I am using zynq Arty-Z7-20 board. Vivado version v2020.2.

I have mentioned steps followed and shared my block design.

1. UART1 --> EMIO

2. UART1 TX [external] --> to pin Y18 (Arty-Z7-20)/JA PMOD, Pin 1 --> constraints file.

3. UART1 RX [external] --> to pin Y19 (Arty-Z7-20)/JA PMOD, Pin 2 --> constrainst file.

ie...

set_property -dict { PACKAGE_PIN Y18 IOSTANDARD LVCMOS33 } [get_ports { ja_r1 }];
set_property -dict { PACKAGE_PIN Y19 IOSTANDARD LVCMOS33 } [get_ports { ja_t1 }];

block design

Screenshot from 2021-03-24 10-03-45.png

4. When I build project without setting UART1 as EMIO it works.

5. Synthesized/Implemented and Generated Bitstream with no issues

6. After setting UART1 as EMIO on build project several time, I have got this critical warnings.

WARNING: [Vivado 12-584] No ports matched 'led[0]'. [/home/jaypatel/fpga/vivado/pps_project/pps_project.srcs/constrs_1/new/pps_const.xdc:23]
WARNING: [Vivado 12-584] No ports matched 'led[1]'. [/home/jaypatel/fpga/vivado/pps_project/pps_project.srcs/constrs_1/new/pps_const.xdc:24]
WARNING: [Vivado 12-584] No ports matched 'led[2]'. [/home/jaypatel/fpga/vivado/pps_project/pps_project.srcs/constrs_1/new/pps_const.xdc:25]
WARNING: [Vivado 12-584] No ports matched 'led[3]'. [/home/jaypatel/fpga/vivado/pps_project/pps_project.srcs/constrs_1/new/pps_const.xdc:26]
WARNING: [Vivado 12-584] No ports matched 'btn[0]'. [/home/jaypatel/fpga/vivado/pps_project/pps_project.srcs/constrs_1/new/pps_const.xdc:29]
WARNING: [Vivado 12-584] No ports matched 'btn[1]'. [/home/jaypatel/fpga/vivado/pps_project/pps_project.srcs/constrs_1/new/pps_const.xdc:30]
WARNING: [Vivado 12-584] No ports matched 'btn[2]'. [/home/jaypatel/fpga/vivado/pps_project/pps_project.srcs/constrs_1/new/pps_const.xdc:31]
WARNING: [Vivado 12-584] No ports matched 'btn[3]'. [/home/jaypatel/fpga/vivado/pps_project/pps_project.srcs/constrs_1/new/pps_const.xdc:32]

 

I don't understand completely because, it works properly when I set UART1 as MIO[48-49].

 

What is the issue in viavdo?

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1 Solution

Accepted Solutions
syedz
Moderator
Moderator
321 Views
Registered: ‎01-16-2013

@JPK17 

 

From the warning, it looks like the tool is not able to find the ports in design that are mentioned at pps_const.xdc (line 23). Can you open the synthesized design and run the following TCL command to check if the ports exist?

get_ports led[0]

get_ports btn[0]

 

--Syed

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------

View solution in original post

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syedz
Moderator
Moderator
322 Views
Registered: ‎01-16-2013

@JPK17 

 

From the warning, it looks like the tool is not able to find the ports in design that are mentioned at pps_const.xdc (line 23). Can you open the synthesized design and run the following TCL command to check if the ports exist?

get_ports led[0]

get_ports btn[0]

 

--Syed

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------

View solution in original post

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JPK17
Observer
Observer
292 Views
Registered: ‎03-11-2021

@syedz 

thanks,

 

set_property -dict { PACKAGE_PIN xxx IOSTANDARD LVCMOS33 } [get_ports { led[0] }];

...

set_property -dict { PACKAGE_PIN xxx IOSTANDARD LVCMOS33 } [get_ports { btn[3] }];

 

I have already defined all the buttons and leds.

It works properly until I set UART1 as EMIO.

After that it starts giving that critical warnings.

 

Regard,

JPK17

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