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Explorer
Explorer
399 Views
Registered: ‎01-15-2019

[UCIO-1] DRC VIOLATION

Hi All,

I'm receiving the following DRC Violation (CRITICAL WARNING): 

UCIO #1 4 out of 31 logical ports have no user assigned specific location constraint (LOC). 
This may cause I/O contention or incompatibility with the board power or connectivity affecting performance,
signal integrity or in extreme cases cause damage to the device or the components to which it is connected.
To correct this violation, specify all pin locations.
This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined.
To allow bitstream creation with unspecified pin locations (not recommended), use this command:
set_property SEVERITY {Warning} [get_drc_checks UCIO-1].
NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file
and add that file as a pre-hook for write_bitstream step for the implementation run.
Problem ports: sfp_1_10g_txp, sfp_1_10g_txn, sfp_0_10g_txp, sfp_0_10g_txn.

 

1) How to fix this violation? How to assign a LOC property to a pin? 

For example, for the sfp_1_10g_txp pin I have the following constraint:

set_property PACKAGE_PIN AH1 [get_ports sfp_1_10g_txn]

Is this not enough?

2) Where can I read about ALL the properties, which could be applied for the pins? 

3) How can I report ALL the properties/attributes, which were applied to a specific pin? 

4) Could the above DRC Violation to lead to a failure of the Bitstream Generation?

Thank you!

 

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1 Reply
Teacher
Teacher
381 Views
Registered: ‎10-23-2018

Re: [UCIO #1] DRC VIOLATION

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