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akboken
Adventurer
Adventurer
6,574 Views
Registered: ‎10-19-2015

USR_ACCESS for mcs file

Hi All,

 

1) I used "set_property BITSTREAM.CONFIG.USR_ACCESS $out [current_design]" to create a timestamp for my bitstream, and I was able to read the USR_ACCESS using JTAG cable.   

When I create a mcs file using the same bitstream and boot the FPGA from flash, I can not read the timestamp value using JTAG. It says the USR_ACCESS is 0.  I am wondering how to add the same timestamp to MCS file ?

 

 

2) How can I read USR_ACCESS from microblaze ? 

 

Thanks,

Akboken. 

 

 

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pratham
Scholar
Scholar
6,549 Views
Registered: ‎06-05-2013

@akboken I think below thread might help you

https://forums.xilinx.com/t5/Virtex-Family-FPGAs/Instantiating-USR-ACCESS-VIRTEX5-for-FPGA-Timestamp-bricks-my/td-p/674261

http://www.xilinx.com/support/documentation/application_notes/xapp497_usr_access.pdf

-Pratham

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akboken
Adventurer
Adventurer
6,516 Views
Registered: ‎10-19-2015

Hi,

 

Thanks.  However, I am still having trouble with my both issues. 

 

1) When I create a MCS file my timestamp info is lost. I think I found the reason why timestamp info get lost.  I have the same problem mentioned here. Basically, when I do "updatemem", that is when I lost my timestamp info. Is this bug not fixed with Vivado 2015.3 version ?

 

2 ) I am not sure how to read USR_ACCESS from a microbalze ? 

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