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Explorer
Explorer
1,977 Views
Registered: ‎07-20-2009

Ultra Scale MIG place error

Hi all,

 

I have a MIG(DDR4) example design in Vivado 2017.1 targeting for kintex ultrascale. After Assigning pin constraints, I tried to implement the design. But following errors occurred.  How to rectify them?

 

ERROR: [Place 30-689] Failed to place BITSLICE_CONTROL cell u_ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control on site BITSLICE_CONTROL_X0Y15 because Instance u_ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control can not be placed in CONTROL of site BITSLICE_CONTROL_X0Y15 because the bel is occupied by u_ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control(port:). This could be caused by bel constraint conflict. Please check if the cell is used correctly in the design.

 

ERROR: [Place 30-691] Failed to place TX_BITSLICE_TRI cell u_ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_TRISTATE[1].GEN_TRISTATE.u_xiphy_tristate/xiphy_bitslice_write on site BITSLICE_TX_X0Y15 because Instance u_ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_TRISTATE[1].GEN_TRISTATE.u_xiphy_tristate/xiphy_bitslice_write can not be placed in TRISTATE_TX_BITSLICE of site BITSLICE_TX_X0Y15 because the bel is occupied by u_ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_TRISTATE[0].GEN_TRISTATE.u_xiphy_tristate/xiphy_bitslice_write(port:). This could be caused by bel constraint conflict. Please check if the cell is used correctly in the design.

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18 Replies
Xilinx Employee
Xilinx Employee
1,965 Views
Registered: ‎09-20-2012

Re: Ultra Scale MIG place error

Hi @anoopjoseph

 

Are you using project mode or non-project mode? Is this a flat design or are you using PR flow? 

 

Can you share DDR4 IP XCI file and the XDC file generated using below command?

 

write_xdc -cell <mig_instance_name> <constr>.xdc

Thanks,
Deepika.
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Explorer
Explorer
1,958 Views
Registered: ‎07-20-2009

Re: Ultra Scale MIG place error

Hi Deepika,

 

Thanks for the reply.

Actually I am in the process of using MIG in non-project flow.

 

For that I created a project and MIG IP in GUI. Then I created a new project in GUI with only .sv files generated from previous project.

Could you please tell me what else I have missed? or is it not the correct way?

 

Regards

Anoop

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Xilinx Employee
Xilinx Employee
1,956 Views
Registered: ‎09-20-2012

Re: Ultra Scale MIG place error

Hi @anoopjoseph

 

So you are trying to use IP RTL instead of IP XCI? 

 

This is not a recommended flow. Is there any specific reason behind using IP RTL instead of its XCI? Can you try using IP XCI instead?

 

MIG PHY is implemented during opt_design in normal flow. It looks like this is not happening when you use RTL instead of XCI.

 

Thanks,
Deepika.
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Explorer
Explorer
1,942 Views
Registered: ‎07-20-2009

Re: Ultra Scale MIG place error

Hi  ,

 

When I used .XCI for DDR4 MIG, it worked. Thanks for your advice.

In non-project flow, can I use the .XCI alone for MIG?

 

Regards

Anoop

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Xilinx Employee
Xilinx Employee
1,928 Views
Registered: ‎09-20-2012

Re: Ultra Scale MIG place error

Hi @anoopjoseph

 

Yes, reading in the XCI using read_ip command should be sufficient. You have use generate_target and synth_ip command if the IP is not generated.

Thanks,
Deepika.
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Explorer
Explorer
1,886 Views
Registered: ‎07-20-2009

Re: Ultra Scale MIG place error

@vemulad,

 

In my existing project( non project mode flow), I have added ddr4_0.xci. After that there is an error after synthesis(Added at last part ), Could you please check what is it? .

 

In the script file for project flow, below steps are already there

generate_target all [get_files *.xci]
synth_ip [get_files *.xci]
get_files -all -of_objects [get_files *.xci]

 

------------------------------------

Part of Vivado log

----------------------------------------

1577 Infos, 412 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:04:12 ; elapsed = 00:06:01 . Memory (MB): peak = 3085.652 ; gain = 1105.926 ; free physical = 151872 ; free virtual = 310089
INFO: [Coretcl 2-1174] Renamed 1142 cell refs.
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Timing 38-2] Deriving generated clocks
INFO: [Common 17-1381] The checkpoint '/home/project/ddr4_0/ddr4_0.dcp' has been generated.
write_checkpoint: Time (s): cpu = 00:00:16 ; elapsed = 00:00:12 . Memory (MB): peak = 3107.699 ; gain = 22.047 ; free physical = 151813 ; free virtual = 310038
ERROR: [Vivado 12-3437] This command only supports sub-design files marked for netlist generation. To enable this functionality, set the GENERATE_SYNTH_CHECKPOINT property to true. If the GENERATE_SYNTH_CHECKPOINT property is marked read-only, then select 'Report IP Status' from the 'Tools' menu, or run the 'report_ip_status' Tcl command to see why the sub-design is locked.
INFO: [Common 17-206] Exiting Vivado at Thu Jan 18 15:11:37 2018...

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Xilinx Employee
Xilinx Employee
1,883 Views
Registered: ‎09-20-2012

Re: Ultra Scale MIG place error

Hi @anoopjoseph

 

Try using below command

 

set_property GENERATE_SYNTH_CHECKPOINT TRUE [get_files .xci]

 

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
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Explorer
Explorer
1,877 Views
Registered: ‎07-20-2009

Re: Ultra Scale MIG place error

 

Could you please tell me at which position I need to give this command ? (like before/after generate_target etc).

Because , I had tried this option. But had failed with another error.

 

Regards

Anoop

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Explorer
Explorer
1,866 Views
Registered: ‎07-20-2009

Re: Ultra Scale MIG place error

@vemulad,

This is the error I got.

-------------------------------------------------------------------

par of vivado log

-------------------------------------------------------------------

USER: Adding IP /home/project/ddr4_0/ddr4_0.xci
# set_property GENERATE_SYNTH_CHECKPOINT TRUE [get_files ddr4_0.xci]
# generate_target all [get_files *.xci]
ERROR: [Vivado 12-3563] The Nested sub-design '/home/project/ddr4_0/ip_0/ddr4_0_microblaze_mcs.xci' can only be generated by its parent sub-design.

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Xilinx Employee
Xilinx Employee
1,844 Views
Registered: ‎09-20-2012

Re: Ultra Scale MIG place error

Hi @anoopjoseph

 

Can you show me the error? Below is the order.

 

set_property GENERATE_SYNTH_CHECKPOINT TRUE [get_files .xci]

generate_target all [get_files *.xci]
synth_ip [get_files *.xci]
get_files -all -of_objects [get_files *.xci]

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
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Explorer
Explorer
1,841 Views
Registered: ‎07-20-2009

Re: Ultra Scale MIG place error

@vemulad,

This is the error I got.

-------------------------------------------------------------------

par of vivado log

-------------------------------------------------------------------

USER: Adding IP /home/project/ddr4_0/ddr4_0.xci
# set_property GENERATE_SYNTH_CHECKPOINT TRUE [get_files ddr4_0.xci]
# generate_target all [get_files *.xci]
ERROR: [Vivado 12-3563] The Nested sub-design '/home/project/ddr4_0/ip_0/ddr4_0_microblaze_mcs.xci' can only be generated by its parent sub-design.

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Xilinx Employee
Xilinx Employee
1,823 Views
Registered: ‎09-20-2012

Re: Ultra Scale MIG place error

Hi @anoopjoseph

 

This flow is working at my end. Can you try specifying the DDR4 IP name in the below command?

 

 generate_target all [get_files ddr4_0.xci]

 

Attached is the log file of my run for your reference.

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
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Explorer
Explorer
1,820 Views
Registered: ‎07-20-2009

Re: Ultra Scale MIG place error

@vemulad

 

 

Thanks I will try.

Then what about other XCIs in design? do they need generate_target?

 

Regards

Anoop

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Xilinx Employee
Xilinx Employee
1,818 Views
Registered: ‎09-20-2012

Re: Ultra Scale MIG place error

Hi @anoopjoseph

 

Yes, if they are not generated. 

 

If this works then you may have to use separate commands for MIG and other IP's.

Thanks,
Deepika.
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Explorer
Explorer
1,806 Views
Registered: ‎07-20-2009

Re: Ultra Scale MIG place error

Hi 

 

 

 

set_property GENERATE_SYNTH_CHECKPOINT TRUE [get_files *.xci]
generate_target all [get_files *.xci]
synth_ip [get_files *.xci]
get_files -all -of_objects [get_files *.xci]

 

Below are the subsequent commands

set_property top ${design_name} [current_fileset]
read_xdc
set default_lib xil_defaultlib
get_property PACKAGE [get_parts ${device}]

synth_design -top ${design_name} -part ${device}
write_checkpoint -force ${design_name}_post_synth.dcp
write_verilog -force ${design_name}.vnet

..........

.........

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Xilinx Employee
Xilinx Employee
1,803 Views
Registered: ‎09-20-2012

Re: Ultra Scale MIG place error

Hi @anoopjoseph

 

Please share your script and log files.

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
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Explorer
Explorer
1,790 Views
Registered: ‎07-20-2009

Re: Ultra Scale MIG place error

Hi @vemulad,

 

I am sorry. I cannot share my original files. (It is controlled). 

This flow was working fine until I add ddr4_0.xci in the file list for synthesis and implementation.

Actually I am not so familiar with non project type flow. Any other problem can you see?

 

If I need to share the files, I need to create a sample environment  and reproduce the problem. Which may take some time.

 

Regards

Anoop

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Explorer
Explorer
1,745 Views
Registered: ‎07-20-2009

Re: Ultra Scale MIG place error

Hi @vemulad

 

When I separated synth_IP commands separately , I could implement my design.

 

Instead of 

generate_target all [get_files *.xci] 

synth_ip [get_files *.xci]

 

I gave

generate_target all [get_files *.xci] 

synth_ip [get_files A.xci] 

synth_ip [get_files B.xci] etc

synth_ip [get_files ddr4_0.xci]

 

Could you please explain why this happened?

What I understood is that I need to separate synth_IP command for DDR4 from other XCI. Is it correct?

 

Is there any single commands to do so?

Like, 

synth_ip [get_files *.xci] //except DDR4

synth_ip [get_files ddr4_0.xci]

 

Regards

Anoop

 

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