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Contributor
Contributor
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Registered: ‎10-01-2010

UltraScale+ FIFO during place_design gives ERROR: [DRC REGP-1605] The FIFO36E2 RDCOUNT[9] pin should not be used

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Vivado 2019.1 place_design is exiting with the following error on an UltraScale+ FIFO36E2:

 

ERROR: [DRC REQP-1605] RDCOUNT9_not_used: rx_framer_i/fifo_i/mem[0].FIFO36E2_inst: The FIFO36E2 RDCOUNT[9] pin should not be used unless READ_WIDTH is 4, 9, 18, 36, or is 72 and RDCOUNT_TYPE is EXTENDED_DATACOUNT or is SIMPLE_DATACOUNT with CLOCK_DOMAINS set to COMMON.

I don't have anything connected to RDCOUNT, but in any case I tried passing the parameters RDCOUNT_TYPE = "SIMPLE_DATACOUNT" and CLOCK_DOMAINS = "COMMON" as suggested to no avail. Here is my FIFO36E2 instantiation:

 

 

 

generate
   for ( m = 0; m < NUM_FIFOS; m++ ) begin : mem

      FIFO36E2 #(
         .CLOCK_DOMAINS             ( "COMMON"                 ),
         .FIRST_WORD_FALL_THROUGH   ( "TRUE"                   ),
         .PROG_FULL_THRESH          ( 511                      ),
         .RDCOUNT_TYPE              ( "SIMPLE_DATACOUNT"       ),
         .READ_WIDTH                ( 72                       ),
         .REGISTER_MODE             ( "REGISTERED"             ),
         .WRITE_WIDTH               ( 72                       ) 
      )
      FIFO36E2_inst (
         // Cascade Signals outputs: Multi-FIFO cascade signals
         .CASDOUT                   (                          ),
         .CASDOUTP                  (                          ),
         .CASNXTEMPTY               (                          ),
         .CASPRVRDEN                (                          ),
         // ECC Signals outputs: Error Correction Circuitry ports
         .DBITERR                   (                          ),
         .ECCPARITY                 (                          ),
         .SBITERR                   (                          ),
         // Read Data outputs: Read output data
         .DOUT                      ( rd_entry[m*72    +:64]   ),
         .DOUTP                     ( rd_entry[m*72+64 +: 8]   ),
         // Status outputs: Flags and other FIFO status outputs
         .EMPTY                     ( empty[m]                 ),
         .FULL                      (                          ),
         .PROGEMPTY                 (                          ),
         .PROGFULL                  ( full_d[m]                ),
         .RDCOUNT                   (                          ),
         .RDERR                     (                          ),
         .RDRSTBUSY                 (                          ),
         .WRCOUNT                   (                          ),
         .WRERR                     (                          ),
         .WRRSTBUSY                 (                          ),
         // Cascade Signals inputs: Multi-FIFO cascade signals
         .CASDIN                    ( 64'h0000000000000000     ),
         .CASDINP                   ( 8'h00                    ),
         .CASDOMUX                  ( 1'b0                     ),
         .CASDOMUXEN                ( 1'b0                     ),
         .CASNXTRDEN                ( 1'b0                     ),
         .CASOREGIMUX               ( 1'b0                     ),
         .CASOREGIMUXEN             ( 1'b0                     ),
         .CASPRVEMPTY               ( 1'b0                     ),
         // ECC Signals inputs: Error Correction Circuitry ports
         .INJECTDBITERR             ( 1'b0                     ),
         .INJECTSBITERR             ( 1'b0                     ),
         // Read Control Signals inputs: Read clock, enable and reset ...
         .RDCLK                     ( aclk_i                   ),
         .RDEN                      ( rd_en                    ),
         .REGCE                     ( 1'b0                     ),
         .RSTREG                    ( 1'b0                     ),
         .SLEEP                     ( 1'b0                     ),
         // Write Control Signals inputs: Write clock and enable 
         .RST                       ( areset_i                 ),
         .WRCLK                     ( aclk_i                   ),
         .WREN                      ( wr_en                    ),
         // Write Data inputs: Write input data
         .DIN                       ( wr_entry[m*72    +:64]   ),
         .DINP                      ( wr_entry[m*72+64 +: 8]   ) 
      );

   end
endgenerate

How can I correct this?

 

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Contributor
Contributor
269 Views
Registered: ‎10-01-2010

Re: UltraScale+ FIFO during place_design gives ERROR: [DRC REGP-1605] The FIFO36E2 RDCOUNT[9] pin should not be used

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Sorry, pilot error. I was looking at a different set of FIFO36E2s than the ones mentioned in the error message. Once I added RDCOUNT_TYPE = "SIMPLE_DATACOUNT" to the correct FIFO, the error went away.

View solution in original post

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Contributor
Contributor
270 Views
Registered: ‎10-01-2010

Re: UltraScale+ FIFO during place_design gives ERROR: [DRC REGP-1605] The FIFO36E2 RDCOUNT[9] pin should not be used

Jump to solution

Sorry, pilot error. I was looking at a different set of FIFO36E2s than the ones mentioned in the error message. Once I added RDCOUNT_TYPE = "SIMPLE_DATACOUNT" to the correct FIFO, the error went away.

View solution in original post

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