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Observer bzuiss
Observer
251 Views
Registered: ‎06-14-2014

Ultrascale + Implementation Strategies

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I have a design on a multi-SLR part with high UltraRAM utilization. (80%+)

Of the numerous implementation strategies, and routing options which would be best suited for this use case?

I am currently utilizing Congestion_SSI_SpreadLogic_High/Low with Vivado 2018.1.

Thanks.

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Xilinx Employee
Xilinx Employee
195 Views
Registered: ‎05-08-2012

Re: Ultrascale + Implementation Strategies

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Hi @bzuiss.

Along with Strategies, you might want to consider running report_qor_suggestions to see if there is anything reported that can help with the quality of results.

I would suggest trying different place_design directives which can be set individually for each run. Specifically to prioritize Block RAM placement there is the EarlyBlockPlacement, and WLDrivenBlockPlacement. Also for SSI designs, there are several SSI_* directives. The full list can be found with the "place_design -help" command.

Also, the place_design -fanout_opt is not enabled by default in 2018.1 (it is for 2018.2), so I would suggest adding this as well.


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1 Reply
Xilinx Employee
Xilinx Employee
196 Views
Registered: ‎05-08-2012

Re: Ultrascale + Implementation Strategies

Jump to solution

Hi @bzuiss.

Along with Strategies, you might want to consider running report_qor_suggestions to see if there is anything reported that can help with the quality of results.

I would suggest trying different place_design directives which can be set individually for each run. Specifically to prioritize Block RAM placement there is the EarlyBlockPlacement, and WLDrivenBlockPlacement. Also for SSI designs, there are several SSI_* directives. The full list can be found with the "place_design -help" command.

Also, the place_design -fanout_opt is not enabled by default in 2018.1 (it is for 2018.2), so I would suggest adding this as well.


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