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msauerpb
Adventurer
Adventurer
582 Views
Registered: ‎01-30-2018

Unplaced elements in Vivado 2020.1.1

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Hi,

I want to test the new Vivado Version 2020.1.1. I opened my existing project (2017.4.1) in Vivado 2020.1. After the conversion I started the implementation run.

During implementation I will get the following error:

Starting Physical Synthesis Task

Phase 1 Physical Synthesis Initialization
INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 2 CPUs
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-6.429 | TNS=-2907.320 |
Phase 1 Physical Synthesis Initialization | Checksum: 1ea87a237

Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 4265.078 ; gain = 0.000
INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to Illegal Netlist: 0.
Ending Physical Synthesis Task | Checksum: 1d866a69f

Time (s): cpu = 00:00:09 ; elapsed = 00:00:05 . Memory (MB): peak = 4265.078 ; gain = 0.000
INFO: [Place 30-746] Post Placement Timing Summary WNS=-0.653. For the most accurate timing information please run report_timing.

Phase 4.2 Post Placement Cleanup
Phase 4.2 Post Placement Cleanup | Checksum: 20bd84663

Time (s): cpu = 00:53:47 ; elapsed = 00:51:32 . Memory (MB): peak = 4265.078 ; gain = 0.000
ERROR: [Place 30-433] Unplaced instances found. If the tcl command place_design -verbose is used, all unplaced instances will be shown below. Otherwise, only 1 example instance will be shown.
Core0/axi_lwl_dio_0/U0/i/do/HiRes.Do_Single[0].do_ctr/o/rResetPinData2_i_1  (LUT4)
Resolution: For technical support on this issue, please visit http://www.xilinx.com/support
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 20bd84663

Time (s): cpu = 00:53:47 ; elapsed = 00:51:33 . Memory (MB): peak = 4265.078 ; gain = 0.000
ERROR: [Place 30-99] Placer failed with error: 'Found unplaced instances.'
Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure.
Ending Placer Task | Checksum: abfb864e

Time (s): cpu = 00:53:48 ; elapsed = 00:51:33 . Memory (MB): peak = 4265.078 ; gain = 0.000
INFO: [Common 17-83] Releasing license: Implementation
122144 Infos, 151 Warnings, 5 Critical Warnings and 3 Errors encountered.
place_design failed
ERROR: [Common 17-69] Command failed: Placer could not place all instances
INFO: [Common 17-206] Exiting Vivado at Wed Nov 18 11:23:24 2020...

 

Can you tell me why I can't implement my design in 2020.1 and in 2017.4 I don't get any error?

Is there a migration guide from 2017.4 to 2020.1 (Vivado and XSDK)?

Thank you for your help.

br

martin

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msauerpb
Adventurer
Adventurer
439 Views
Registered: ‎01-30-2018

I have to deinstall the 2020.1 version and work again with 2017.4. Becaus I don't get a solution for my problem.

br

martin

View solution in original post

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5 Replies
dpaul24
Scholar
Scholar
573 Views
Registered: ‎08-07-2014

@msauerpb ,

With Vivado update IP Core updates are also available, depending on the IP core/s used in the project.

If you are using any Xilinx IP core, then please check manually if that IP core/s can be updated and re-generate that IP core/s. Only after that proceed to synth and impl.

------------FPGA enthusiast------------
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msauerpb
Adventurer
Adventurer
555 Views
Registered: ‎01-30-2018
@dpaul24,

before I start the synthesis run, I did an upgrade of all of our IP cores, so the newest version is used.

BR
martin
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surajc
Xilinx Employee
Xilinx Employee
539 Views
Registered: ‎01-30-2019

Hi @msauerpb 

Could you provide us with place_design -verbose log? 

 

 

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msauerpb
Adventurer
Adventurer
506 Views
Registered: ‎01-30-2018

Hi,

attached you will find the runme.log from the implementation step.

The options are:

Bild_2020-11-19_063432.png

 

BR

martin

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msauerpb
Adventurer
Adventurer
440 Views
Registered: ‎01-30-2018

I have to deinstall the 2020.1 version and work again with 2017.4. Becaus I don't get a solution for my problem.

br

martin

View solution in original post

0 Kudos