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Visitor
Visitor
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Registered: ‎12-17-2009

Unroutable Placement! A GT / MMCM component pair

I'm getting a placer error message on an unroutable clock from my GTXE2_CHANNEL cell to a MMCM even though they both cells are in the same clock region: X0Y4.  This is on a Kintex xc7k325tffg676 device.  I am using Vivado ver. 2018.2.  Same error happens in a 2016 version of Vivado.  I have searched these forums and seen some discussion about differences on Virtex vs Kintex parts where a Kintex device cannot route from a TXOUTCLK directly to an MMCM input without a BUFG.  If this is the issue here, then the error message is inaccurate and cryptic.

 

ERROR: [Place 30-139] Unroutable Placement! A GT / MMCM component pair is not placed in a routable site pair. The GT component can use the dedicated path between the GT and the MMCM if both are placed in the same clock region. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
< set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets i_gtx_ip_top/gtx_ip_top_desc_i/gtx_wrapper_i/genblk1.gtx_phy_top_u0/gtwizard_v2_4_1_inst/gt0_gtwizard_v2_4_1_i/TXOUTCLK_0] >

i_gtx_ip_top/gtx_ip_top_desc_i/gtx_wrapper_i/genblk1.gtx_phy_top_u0/gtwizard_v2_4_1_inst/gt0_gtwizard_v2_4_1_i/gtxe2_i (GTXE2_CHANNEL.TXOUTCLK) is locked to GTXE2_CHANNEL_X0Y4
i_gtx_ip_top/gtx_ip_top_desc_i/gtx_wrapper_i/genblk1.gtx_phy_top_u0/genblk5.mmcm_gtx/inst/mmcm_adv_inst (MMCME2_ADV.CLKIN1) is locked to MMCME2_ADV_X0Y4

The above error could possibly be related to other connected instances. Following is a list of
all the related clock rules and their respective instances.

Clock Rule: rule_gtxcommon_gtxchannel
Status: PASS
Rule Description: A GTXCommon driving a GTXChannel must both be in the same clock region
i_gtx_ip_top/gtx_ip_top_desc_i/gtx_wrapper_i/genblk1.gtx_phy_top_u0/gtwizard_v2_4_1_inst/genblk2.gtxe2_common_0_i (GTXE2_COMMON.QPLLOUTCLK) is locked to GTXE2_COMMON_X0Y1
i_gtx_ip_top/gtx_ip_top_desc_i/gtx_wrapper_i/genblk1.gtx_phy_top_u0/gtwizard_v2_4_1_inst/gt0_gtwizard_v2_4_1_i/gtxe2_i (GTXE2_CHANNEL.QPLLCLK) is locked to GTXE2_CHANNEL_X0Y4

Clock Rule: rule_mmcm_bufg
Status: PASS
Rule Description: An MMCM driving a BUFG must be placed on the same half side (top/bottom) of the device
i_gtx_ip_top/gtx_ip_top_desc_i/gtx_wrapper_i/genblk1.gtx_phy_top_u0/genblk5.mmcm_gtx/inst/mmcm_adv_inst (MMCME2_ADV.CLKFBOUT) is locked to MMCME2_ADV_X0Y4
i_gtx_ip_top/gtx_ip_top_desc_i/gtx_wrapper_i/genblk1.gtx_phy_top_u0/genblk5.mmcm_gtx/inst/clkf_buf (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y19

Clock Rule: rule_bufds_gtxcommon_intelligent_pin
Status: PASS
Rule Description: A BUFDS driving a GTXCommon must both be placed in the same or adjacent clock region
(top/bottom)
i_gtx_ip_top/gtx_ip_top_desc_i/gtx_wrapper_i/genblk1.gtx_phy_top_u0/genblk3.lvds_gtx_buf (IBUFDS_GTE2.O) is provisionally placed by clockplacer on IBUFDS_GTE2_X0Y0
i_gtx_ip_top/gtx_ip_top_desc_i/gtx_wrapper_i/genblk1.gtx_phy_top_u0/gtwizard_v2_4_1_inst/genblk2.gtxe2_common_0_i (GTXE2_COMMON.GTREFCLK0) is locked to GTXE2_COMMON_X0Y1

 

 

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Xilinx Employee
Xilinx Employee
1,031 Views
Registered: ‎07-16-2008

回复: Unroutable Placement! A GT / MMCM component pair

First of all, in 7-series devices, GT's TXOUTCLK is able to drive MMCM directly in the same clock region. Please refer to UG472, Table 1-1.

table.JPG

 

Secondly, it's not true that the current placement of the GT and MMCM are in the same clock region.

MMCME2_ADV_X0Y4 is in Clock Region X0Y4.

whereas GTXE2_CHANNEL_X0Y4 is in Clock Region X1Y4.

As shown in the Device Window in Vivado IDE, MMCM is marked in magenta and GT is marked in yellow.

clock_region.jpg

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Visitor
Visitor
972 Views
Registered: ‎12-17-2009

回复: Unroutable Placement! A GT / MMCM component pair

thank you, but how does one ID the clock region of a component besides having to look it up on a floorplan?  Is there a chart/table published somewhere that conveys this info?  I always thought that the postfix on the component naming indicated this, but I guess not.  And... why doesn't Vivado report the component's clock region in the error messages, or did I miss something?  

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎07-16-2008

回复: Unroutable Placement! A GT / MMCM component pair

The coordinate of physical site is not necessarily in accordance with the one of its clock region.

There's no table that explicitly lists clock region for every component in each device family.

 

You can find the clock region resource by

1. open a Vivado project

2. open synthesized/implemented design

3. launch Clock Regions window (Window > Clock Regions)

4. select one clock region and check the 'Sites' tab in Clock Region Properties window

 

Or, if you would like to locate the clock region for a specific site, 

1. open the design in Vivado project

2. ctrl+F to open the Find dialog box and set the search criteria to find a matching site name

3. select the site in Find Results and cross check its clock region in Device window

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Visitor
Visitor
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Registered: ‎12-17-2009

回复: Unroutable Placement! A GT / MMCM component pair

sounds awfully complicated just to get a component's clock region.  Why not change the tool to make it easier by listing the clock region as a property of the component?  Just sayin.

 

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Moderator
Moderator
921 Views
Registered: ‎01-16-2013

回复: Unroutable Placement! A GT / MMCM component pair

@davemac22

 

After opt_design, you can run place_ports command which will run clock and IO placement step first. then run place_design. 

If port placement fails, the placement is saved to memory to allow failure analysis. For more information, run place_ports -help from the Vivado Tcl command prompt. 

 

With place_ports, you should be able to see the clock region of the component in its properties window. 

 

--Syed

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Xilinx Employee
Xilinx Employee
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Registered: ‎07-16-2008

回复: Unroutable Placement! A GT / MMCM component pair


@davemac22  已写:

sounds awfully complicated just to get a component's clock region.  Why not change the tool to make it easier by listing the clock region as a property of the component?  Just sayin.

 


It's true that you can query the CLOCK_REGION property of a physical site.

get_property CLOCK_REGION [get_sites GTXE2_CHANNEL_X0Y4 ]

 

You need to either run the Tcl command in the design context or in an empty I/O Planning Project.

We recommend that you do I/O and clock resource planning as one of the first steps of your design.

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