1 Solution
Accepted Solutions
Thanks for helping
It appears that you want to bring the Clock into the device and connect directly to a PLL, in this case in the bottom of the device also. The tools will route the clock through a BUFIO2 to the PLL and the Feedback Clock will route through a BUFG to a BUFIO2_FB placed adjacent to the associated BUFIO2. This will provide you with a clock that is correctly routed and will use the correct feedback to correctly remove the clock insertion delay.
I have 16 LVDS DDR data channels connected to bottom of the device and 1 LVDS clock that i want to use to deserialize data. To do that i'm connecting it to PLL to generate bit and word clocks.
Problem is that during implementation, compiler chooses PLL on the other side of the device. I'm not LOCing any of the primitives i'm using besides MCB part which LOCed itself without my help.
On the image below you can see screenshot from the FPGA editor. Red spots at the bottom are my RX channel with Data and Clock ports.
On the left is B3 clock which is a master logic clock that's used to start design, and clock the MCB PLL, which is connected to right edge of the device.
This red dot at the top is PLL_ADV instance with was choosen by tools during compilation, it's quite far from the place it's needed since it's primarly used to deserialize incoming data from the bottom.
Maybe i should force placement of the PLL_ADV to somewhere in the bottom half of the device?
If this is a good idea which one should i pick?
I don't want to use BUFIO2 because in near future i will need 32 LVDS input channels that will span to more than one BUFIO region...
I can upload *ncd file if it would help ...
From a picture I have laying around it just shows a DCM but this will also apply to the PLL.
If you coded the PAD (IBUF) to connect directly to the PLL then the PLL to connect to a BUFG and finally the BUFG to the PLL Feedback, this circuit should be implemented automatically.
The BUFIO2 is used so the input will match the delay of the BUFIO2FB in the feedback path. You will not be using the BUFIO2 to directly capture the data, just to correctly implement the PLL so that it will remove the clock insertion delay.
Thanks for helping.
I understood that i should insert a BUFIO2 local clock buffer to ease routiing between PAD and PLL, so i've done something like this:
Unfortunately i'm still gettings the same error inthe Maping :
ERROR:Place:1108 - A clock IOB / BUFGMUX clock component pair have been found that are not placed at an optimal clock IOB / BUFGMUX site pair. The clock IOB component <A0_DCLK_P> is placed at site <AC16>. The corresponding BUFG component <data_buffer_inst/data_standarizer/data_rx_inst/clk_rx_buff<0>_BUFG> is placed at site <BUFGMUX_X2Y1>. There is only a select set of IOBs that can use the fast path to the Clocker buffer, and they are not being used. You may want to analyze why this problem exists and correct it. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this message to a WARNING and allow your design to continue. However, the use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. A list of all the COMP.PINs used in this clock placement rule is listed below. These examples can be used directly in the .ucf file to override this clock rule. < NET "A0_DCLK_P" CLOCK_DEDICATED_ROUTE = FALSE; >
Thanks!
This is the error you need to fix. Is there a BUFG between the PAD and the BUFG?
I didn't instantiate any BUFG between PAD and PLL, because this i what you meant i guess :).
BUT! After inspecting in the FPGA Editor i found that Compiler inserted A BUFGM to one the pins of the differential clock:
From UG615 about IBUGDS:
Put all I/O components on the top-level of the design to help facilitate hierarchical design methods. Connect the I
port directly to the top-level "master" input port of the design, the IB port to the top-level "slave" input port and
the O port to an MMCM, BUFG or logic in which this input is to source. Some synthesis tools infer the BUFG
automatically if necessary, when connecting an IBUFG to the clock resources of the FPGA. Specify the desired
generic/defparam values in order to configure the proper behavior of the buffer.
I didn't do thing from the first sentence - i instantiated a IBUFG in the module deeper than TOP in my design, and i guess this might be the reason Compiler is inserting a BUFGM in my clock path.
I will move this primite (IBUFGDS) to top and see if it will help
UPDATE
I moved IBUFGDS to top level entity, but unfortunaltey it didn't help. I still have the same error:
ERROR:Place:1108 - A clock IOB / BUFGMUX clock component pair have been found that are not placed at an optimal clock IOB / BUFGMUX site pair. The clock IOB component <A3_DCLK_P> is placed at site <AJ17>. The corresponding BUFG component <src_clk_buff_BUFG> is placed at site <BUFGMUX_X2Y2>. There is only a select set of IOBs that can use the fast path to the Clocker buffer, and they are not being used. You may want to analyze why this problem exists and correct it. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this message to a WARNING and allow your design to continue. However, the use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. A list of all the COMP.PINs used in this clock placement rule is listed below. These examples can be used directly in the .ucf file to override this clock rule. < NET "A3_DCLK_P" CLOCK_DEDICATED_ROUTE = FALSE; >
Additionaly I tried using 3 different clocks , i all cases a misterious BUFG is generated
I tried those differential pairs:
NET "A0_DCLK_N" LOC = "AD16"; #IO_L29N_GCLK2_2 NET "A0_DCLK_P" LOC = "AC16"; #IO_L29P_GCLK3_2 NET "A1_DCLK_N" LOC = "AG16"; #IO_L30N_GCLK0_USERCCLK_2 NET "A1_DCLK_P" LOC = "AF16"; #IO_L30P_GCLK1_D13_2 NET "A2_DCLK_N" LOC = "AK16"; #IO_L31N_GCLK30_D15_2 NET "A2_DCLK_P" LOC = "AH16"; #IO_L31P_GCLK31_D14_2 NET "A3_DCLK_N" LOC = "AK17"; #IO_L32N_GCLK28_2 NET "A3_DCLK_P" LOC = "AJ17"; #IO_L32P_GCLK29_2
What's interesing, this IBUFG is inserted only in the Positive node of the diff clock...
" use floor planning tool to isolate the BUFG that is causing this issue "
Is there any 'algorithm' i can use to find this particular BUFG?
For example in this routing conflict:
Routing Conflict 16: Net:data_buffer_inst/data_standarizer/clk_ser_del_o on pin IOCLK1 on location IODELAY_X34Y3 Net:data_buffer_inst/clk_ser on pin CLK1 on location ILOGIC_X34Y3
Maybe i should check in the datasheet which BUFG should be IODELAY_X34Y3 connected to?
EDIT
I tried looking for it this way:
After Map process i've opened FPGA Editor and searched for clk_ser and clk_ser_del which seems to be be causing all routing conflicts, the BUFG they are connected to is :
comp "data_buffer_inst/data_standarizer/data_rx_inst/pll_dyn_top_int/BUFG_CLK1", site "BUFGMUX_X2Y2", type = BUFG (RPM grid X169Y390)
This is how it looks like in the FPGA Editor:
Weird thing is, this BUFG_X2Y2 seems to be already placed in the top half of the device (according to UG382)
I tried to follow your hints, and i come up with the clock configuration as in the image:
I buffered two fast serial clock outputs (normal and 180 degrees shifted for DDR signal) from the PLL (output 0 and 1) through BUFFPLL to IODELAYs inputs IOCLK0 and IOCLK1,
Third slower parallel clock from PLL (output 2) goes through BUFG to CLK input of the IODELAYs
Routing conflicts dissappeared, new error showed up :
ERROR:Place:1286 - Placer has detected a BUFIO2 component < data_buffer_inst/data_standarizer/data_rx_inst/pll_dyn_top_int/BUFIO2_inst > driving component < data_buffer_inst/data_standarizer/data_rx_inst/pll_dyn_top_int/PLL_ADV_inst > (on pin < CLKIN1 >) which is not associated with an IOB component. Automatic clock placement of components not associated with an IOB is not supported. If the load component is an IODELAY, the user can LOC the IODELAY and BUFIO2 to the same half-bank and re-run placer.
Is this the error you expected?
Thanks again.
From what i understood :
If i don't wan't to use primitive IOSERDES2 to deserialize incoming data i can't use BUFIO2 or BUFIO2_PLL to clock IODELAY2 or IDDR2, i cant only use global clocking network using BUFG's
I have to route one of the 3 clocks i need to power IODELAY through top half of the device, to do that i need set LOC attribute to this BUFG to any of the BUFG's locaated in the top half.
Is that correct?
I drew a schematic how i'm gonna connect all clocks:
