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Adventurer
Adventurer
14,667 Views
Registered: ‎12-21-2011

Unroutable design - ERROR:Route:472

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Hello again.

 

I'm trying to Implement my design for Spartan-6 (xc6slx150t--3fgg900). It's my first big design that uses a lot of device-specific parts like PLL's ,MCB, Block RAMs, IODELAYS, BUFG's and so on. I really don't know how i can resolve this problem. I'm looking for a place to start ...

 

I read ug382 with the clocking resources for Spartan 6 but it's a bit to heavy for a beginner ...

 

My design consists of two parts:

 

1. Memory Controller Block with DDR3 memory connected to Bank 1. It uses it's own PLL to clock itself, i'm feeding input clock to that module from LVDS clock connected to GCLK24 and GCLK25, through IBUFGDS to CLKIN if the MCB_PLL. UCF for DDR chip is taken from that generated by CoreGen. If only this module is in the project it implements without errors/

 

2. Deserializers connected to bottom part of the device (see attached UCF ,pins A0_DA0_N-A3_FCLK_P (lines 65 - 185) . Data lines are read though IBUFDS then IODELAY2 then IDDR. This part is clocked by 4 clock generated by the PLL_ADV instance.

 

PLL_ADV have it's input connected to pins GCLK2/GCLK3 (A0_DCLK_P/A0_DCLK_N), through IBUFGDS. Feedback of the PLL_ADV is through BUFG_FB. It outputs 4 clocks: clk_par, clk_ser, clk_ser_del, clk_ser_2x with programmable parameters.

 

Those 4 clocks are clocking whole logic of the design including user - interface of the MCB.

 

With this configuration i'm there is an error in the MAP process:

 

ERROR:Place:1108 - A clock IOB / BUFGMUX clock component pair have been found
   that are not placed at an optimal clock IOB / BUFGMUX site pair. The clock
   IOB component <A0_DCLK_P> is placed at site <AC16>. The corresponding BUFG
   component
   <data_buffer_inst/data_standarizer/data_rx_inst/pll_dyn_top_int/BUFG_IN> is
   placed at site <BUFGMUX_X2Y2>. There is only a select set of IOBs that can
   use the fast path to the Clocker buffer, and they are not being used. You may
   want to analyze why this problem exists and correct it. If this sub optimal
   condition is acceptable for this design, you may use the
   CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this message to a
   WARNING and allow your design to continue. However, the use of this override
   is highly discouraged as it may lead to very poor timing results. It is
   recommended that this error condition be corrected in the design. A list of
   all the COMP.PINs used in this clock placement rule is listed below. These
   examples can be used directly in the .ucf file to override this clock rule.
   < NET "A0_DCLK_P" CLOCK_DEDICATED_ROUTE = FALSE; >

 and when i put this rule from last line of the error i'm getting Error with the number in the topic of this post.

 

One of ideas is to connect outputs of the PLL_ADV clocking the deserializers to BUFGs, does it make any sense?

 

Does anyone have idea how i can start to debug this. Or where can i find information about using clocking resources in the Xilinx FPGAs ....

 

Thanks for any help

 

p.s. You can download my Synthesis report in the PDF format HERE, and Image of Spartan Clock Pin Layout from UG382 HERE

 

 

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Adventurer
Adventurer
8,590 Views
Registered: ‎12-21-2011
great, i'm going home right now but i will try this solution first thing tomorrow morning:D

thanks!
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Historian
Historian
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Registered: ‎02-25-2008

@llewis wrote:

The quickest way to find out what combination of clocks will work is to load FPGA Edtior, add 3 BUFGs and then connect them to the IODELAY and ILOGIC.  I just tried a few combinations and found that the 3 BUFGs do not work either.  The intent for these circuits was to be used with the BUFIO2 or BUFPLL so most advanced clocking combinations will require the use of them.  


How about this radical suggestion:

 

Instead of making each Xilinx customer -- the design engineers who specify these devices -- play games with the tools to figure out what magic combination of things will work, why doesn't Xilinx document all of this stuff correctly?

 

I wasted almost two weeks trying to figure out the magic combination of buffers and such to make a simpler mechanism work. It took the webcase support person a week to figure it all out.

 

Why?

 

BECAUSE IT'S NOT DOCUMENTED.

And this lack of quality documentation is not acceptable.

 

Xilinx documentation really sucks. Yes, indeed.

 

If the user can't figure out how to make a feature work, for all intents and purposes that feature doesn't exist. And as such the user will look for an alternate solution, most likely involving a different FPGA vendor.

----------------------------Yes, I do this for a living.
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Adventurer
Adventurer
8,573 Views
Registered: ‎12-21-2011

how does the Xilinx's documentation compares to other verndors Altera, Lattice and others?

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Adventurer
Adventurer
8,563 Views
Registered: ‎12-21-2011

After applying all hints , my design is finally routable !

 

But the next step : "Generate Programming File" generates many errors and fails :(

 

Started : "Generate Programming File".
Running bitgen...
Command Line: bitgen -intstyle ise -f m_k40_top.ut m_k40_top.ncd
ERROR:PhysDesignRules:1765 - Issue with pin connections and/or configuration on
   block:<data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[8].inst_ser
   2par/inst_delay>:<IODELAY2_IODELAY2>.  For DELAY_SRC IO programming the T
   input pin of IODELAY2 must be connected.
ERROR:PhysDesignRules:1768 - Issue with pin connections and/or configuration on
   block:<data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[8].inst_ser
   2par/inst_delay>:<IODELAY2_IODELAY2>.  For DELAY_SRC programming ODATAIN or
   IO the ODATAIN input pin of IODELAY2 must be connected.
ERROR:PhysDesignRules:1765 - Issue with pin connections and/or configuration on
   block:<data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[10].inst_se
   r2par/inst_delay>:<IODELAY2_IODELAY2>.  For DELAY_SRC IO programming the T
   input pin of IODELAY2 must be connected.
ERROR:PhysDesignRules:1768 - Issue with pin connections and/or configuration on
   block:<data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[10].inst_se
   r2par/inst_delay>:<IODELAY2_IODELAY2>.  For DELAY_SRC programming ODATAIN or
   IO the ODATAIN input pin of IODELAY2 must be connected.
ERROR:PhysDesignRules:1765 - Issue with pin connections and/or configuration on
   block:<data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[9].inst_ser
   2par/inst_delay>:<IODELAY2_IODELAY2>.  For DELAY_SRC IO programming the T
   input pin of IODELAY2 must be connected.
ERROR:PhysDesignRules:1768 - Issue with pin connections and/or configuration on
   block:<data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[9].inst_ser
   2par/inst_delay>:<IODELAY2_IODELAY2>.  For DELAY_SRC programming ODATAIN or
   IO the ODATAIN input pin of IODELAY2 must be connected.
ERROR:PhysDesignRules:1765 - Issue with pin connections and/or configuration on
   block:<data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[11].inst_se
   r2par/inst_delay>:<IODELAY2_IODELAY2>.  For DELAY_SRC IO programming the T
   input pin of IODELAY2 must be connected.
ERROR:PhysDesignRules:1768 - Issue with pin connections and/or configuration on
   block:<data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[11].inst_se
   r2par/inst_delay>:<IODELAY2_IODELAY2>.  For DELAY_SRC programming ODATAIN or
   IO the ODATAIN input pin of IODELAY2 must be connected.
ERROR:PhysDesignRules:1765 - Issue with pin connections and/or configuration on
   block:<data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[0].inst_ser
   2par/inst_delay>:<IODELAY2_IODELAY2>.  For DELAY_SRC IO programming the T
   input pin of IODELAY2 must be connected.
ERROR:PhysDesignRules:1768 - Issue with pin connections and/or configuration on
   block:<data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[0].inst_ser
   2par/inst_delay>:<IODELAY2_IODELAY2>.  For DELAY_SRC programming ODATAIN or
   IO the ODATAIN input pin of IODELAY2 must be connected.
ERROR:PhysDesignRules:1765 - Issue with pin connections and/or configuration on
   block:<data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[12].inst_se
   r2par/inst_delay>:<IODELAY2_IODELAY2>.  For DELAY_SRC IO programming the T
   input pin of IODELAY2 must be connected.
ERROR:PhysDesignRules:1768 - Issue with pin connections and/or configuration on
   block:<data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[12].inst_se
   r2par/inst_delay>:<IODELAY2_IODELAY2>.  For DELAY_SRC programming ODATAIN or
   IO the ODATAIN input pin of IODELAY2 must be connected.
ERROR:PhysDesignRules:1765 - Issue with pin connections and/or configuration on
   block:<data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[1].inst_ser
   2par/inst_delay>:<IODELAY2_IODELAY2>.  For DELAY_SRC IO programming the T
   input pin of IODELAY2 must be connected.
ERROR:PhysDesignRules:1768 - Issue with pin connections and/or configuration on
   block:<data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[1].inst_ser
   2par/inst_delay>:<IODELAY2_IODELAY2>.  For DELAY_SRC programming ODATAIN or
   IO the ODATAIN input pin of IODELAY2 must be connected.
ERROR:PhysDesignRules:1765 - Issue with pin connections and/or configuration on
   block:<data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[13].inst_se
   r2par/inst_delay>:<IODELAY2_IODELAY2>.  For DELAY_SRC IO programming the T
   input pin of IODELAY2 must be connected.
ERROR:PhysDesignRules:1768 - Issue with pin connections and/or configuration on
   block:<data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[13].inst_se
   r2par/inst_delay>:<IODELAY2_IODELAY2>.  For DELAY_SRC programming ODATAIN or
   IO the ODATAIN input pin of IODELAY2 must be connected.
ERROR:PhysDesignRules:1765 - Issue with pin connections and/or configuration on
   block:<data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[2].inst_ser
   2par/inst_delay>:<IODELAY2_IODELAY2>.  For DELAY_SRC IO programming the T
   input pin of IODELAY2 must be connected.
ERROR:PhysDesignRules:1768 - Issue with pin connections and/or configuration on
   block:<data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[2].inst_ser
   2par/inst_delay>:<IODELAY2_IODELAY2>.  For DELAY_SRC programming ODATAIN or
   IO the ODATAIN input pin of IODELAY2 must be connected.
ERROR:PhysDesignRules:1765 - Issue with pin connections and/or configuration on
   block:<data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[14].inst_se
   r2par/inst_delay>:<IODELAY2_IODELAY2>.  For DELAY_SRC IO programming the T
   input pin of IODELAY2 must be connected.
ERROR:PhysDesignRules:1768 - Issue with pin connections and/or configuration on
   block:<data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[14].inst_se
   r2par/inst_delay>:<IODELAY2_IODELAY2>.  For DELAY_SRC programming ODATAIN or
   IO the ODATAIN input pin of IODELAY2 must be connected.
ERROR:PhysDesignRules:1765 - Issue with pin connections and/or configuration on
   block:<data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[3].inst_ser
   2par/inst_delay>:<IODELAY2_IODELAY2>.  For DELAY_SRC IO programming the T
   input pin of IODELAY2 must be connected.
ERROR:PhysDesignRules:1768 - Issue with pin connections and/or configuration on
   block:<data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[3].inst_ser
   2par/inst_delay>:<IODELAY2_IODELAY2>.  For DELAY_SRC programming ODATAIN or
   IO the ODATAIN input pin of IODELAY2 must be connected.
ERROR:PhysDesignRules:1765 - Issue with pin connections and/or configuration on
   block:<data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[15].inst_se
   r2par/inst_delay>:<IODELAY2_IODELAY2>.  For DELAY_SRC IO programming the T
   input pin of IODELAY2 must be connected.
ERROR:PhysDesignRules:1768 - Issue with pin connections and/or configuration on
   block:<data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[15].inst_se
   r2par/inst_delay>:<IODELAY2_IODELAY2>.  For DELAY_SRC programming ODATAIN or
   IO the ODATAIN input pin of IODELAY2 must be connected.
ERROR:PhysDesignRules:1765 - Issue with pin connections and/or configuration on
   block:<data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[4].inst_ser
   2par/inst_delay>:<IODELAY2_IODELAY2>.  For DELAY_SRC IO programming the T
   input pin of IODELAY2 must be connected.
ERROR:PhysDesignRules:1768 - Issue with pin connections and/or configuration on
   block:<data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[4].inst_ser
   2par/inst_delay>:<IODELAY2_IODELAY2>.  For DELAY_SRC programming ODATAIN or
   IO the ODATAIN input pin of IODELAY2 must be connected.
ERROR:PhysDesignRules:1765 - Issue with pin connections and/or configuration on
   block:<data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[5].inst_ser
   2par/inst_delay>:<IODELAY2_IODELAY2>.  For DELAY_SRC IO programming the T
   input pin of IODELAY2 must be connected.
ERROR:PhysDesignRules:1768 - Issue with pin connections and/or configuration on
   block:<data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[5].inst_ser
   2par/inst_delay>:<IODELAY2_IODELAY2>.  For DELAY_SRC programming ODATAIN or
   IO the ODATAIN input pin of IODELAY2 must be connected.
ERROR:PhysDesignRules:1765 - Issue with pin connections and/or configuration on
   block:<data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[6].inst_ser
   2par/inst_delay>:<IODELAY2_IODELAY2>.  For DELAY_SRC IO programming the T
   input pin of IODELAY2 must be connected.
ERROR:PhysDesignRules:1768 - Issue with pin connections and/or configuration on
   block:<data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[6].inst_ser
   2par/inst_delay>:<IODELAY2_IODELAY2>.  For DELAY_SRC programming ODATAIN or
   IO the ODATAIN input pin of IODELAY2 must be connected.
ERROR:PhysDesignRules:1765 - Issue with pin connections and/or configuration on
   block:<data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[7].inst_ser
   2par/inst_delay>:<IODELAY2_IODELAY2>.  For DELAY_SRC IO programming the T
   input pin of IODELAY2 must be connected.
ERROR:PhysDesignRules:1768 - Issue with pin connections and/or configuration on
   block:<data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[7].inst_ser
   2par/inst_delay>:<IODELAY2_IODELAY2>.  For DELAY_SRC programming ODATAIN or
   IO the ODATAIN input pin of IODELAY2 must be connected.
ERROR:PhysDesignRules:2003 - Unsupported clocking structure. Inversion
   programming for block
   data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[0].inst_ser2par/id
   dr_q2 pin CLK0 (INVERTED) must match programming for block
   data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[0].inst_ser2par/in
   st_delay pin IOCLK0 (NOT INVERTED) when using a shared clock inversion
   source.
ERROR:PhysDesignRules:2003 - Unsupported clocking structure. Inversion
   programming for block
   data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[0].inst_ser2par/id
   dr_q2 pin CLK1 (NOT INVERTED) must match programming for block
   data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[0].inst_ser2par/in
   st_delay pin IOCLK1 (INVERTED) when using a shared clock inversion source.
ERROR:PhysDesignRules:2003 - Unsupported clocking structure. Inversion
   programming for block
   data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[9].inst_ser2par/id
   dr_q2 pin CLK0 (INVERTED) must match programming for block
   data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[9].inst_ser2par/in
   st_delay pin IOCLK0 (NOT INVERTED) when using a shared clock inversion
   source.
ERROR:PhysDesignRules:2003 - Unsupported clocking structure. Inversion
   programming for block
   data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[9].inst_ser2par/id
   dr_q2 pin CLK1 (NOT INVERTED) must match programming for block
   data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[9].inst_ser2par/in
   st_delay pin IOCLK1 (INVERTED) when using a shared clock inversion source.
ERROR:PhysDesignRules:2003 - Unsupported clocking structure. Inversion
   programming for block
   data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[1].inst_ser2par/id
   dr_q2 pin CLK0 (INVERTED) must match programming for block
   data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[1].inst_ser2par/in
   st_delay pin IOCLK0 (NOT INVERTED) when using a shared clock inversion
   source.
ERROR:PhysDesignRules:2003 - Unsupported clocking structure. Inversion
   programming for block
   data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[1].inst_ser2par/id
   dr_q2 pin CLK1 (NOT INVERTED) must match programming for block
   data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[1].inst_ser2par/in
   st_delay pin IOCLK1 (INVERTED) when using a shared clock inversion source.
ERROR:PhysDesignRules:2003 - Unsupported clocking structure. Inversion
   programming for block
   data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[2].inst_ser2par/id
   dr_q2 pin CLK0 (INVERTED) must match programming for block
   data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[2].inst_ser2par/in
   st_delay pin IOCLK0 (NOT INVERTED) when using a shared clock inversion
   source.
ERROR:PhysDesignRules:2003 - Unsupported clocking structure. Inversion
   programming for block
   data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[2].inst_ser2par/id
   dr_q2 pin CLK1 (NOT INVERTED) must match programming for block
   data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[2].inst_ser2par/in
   st_delay pin IOCLK1 (INVERTED) when using a shared clock inversion source.
ERROR:PhysDesignRules:2003 - Unsupported clocking structure. Inversion
   programming for block
   data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[3].inst_ser2par/id
   dr_q2 pin CLK0 (INVERTED) must match programming for block
   data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[3].inst_ser2par/in
   st_delay pin IOCLK0 (NOT INVERTED) when using a shared clock inversion
   source.
ERROR:PhysDesignRules:2003 - Unsupported clocking structure. Inversion
   programming for block
   data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[3].inst_ser2par/id
   dr_q2 pin CLK1 (NOT INVERTED) must match programming for block
   data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[3].inst_ser2par/in
   st_delay pin IOCLK1 (INVERTED) when using a shared clock inversion source.
ERROR:PhysDesignRules:2003 - Unsupported clocking structure. Inversion
   programming for block
   data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[4].inst_ser2par/id
   dr_q2 pin CLK0 (INVERTED) must match programming for block
   data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[4].inst_ser2par/in
   st_delay pin IOCLK0 (NOT INVERTED) when using a shared clock inversion
   source.
ERROR:PhysDesignRules:2003 - Unsupported clocking structure. Inversion
   programming for block
   data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[4].inst_ser2par/id
   dr_q2 pin CLK1 (NOT INVERTED) must match programming for block
   data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[4].inst_ser2par/in
   st_delay pin IOCLK1 (INVERTED) when using a shared clock inversion source.
ERROR:PhysDesignRules:2003 - Unsupported clocking structure. Inversion
   programming for block
   data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[5].inst_ser2par/id
   dr_q2 pin CLK0 (INVERTED) must match programming for block
   data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[5].inst_ser2par/in
   st_delay pin IOCLK0 (NOT INVERTED) when using a shared clock inversion
   source.
ERROR:PhysDesignRules:2003 - Unsupported clocking structure. Inversion
   programming for block
   data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[5].inst_ser2par/id
   dr_q2 pin CLK1 (NOT INVERTED) must match programming for block
   data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[5].inst_ser2par/in
   st_delay pin IOCLK1 (INVERTED) when using a shared clock inversion source.
ERROR:PhysDesignRules:2003 - Unsupported clocking structure. Inversion
   programming for block
   data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[6].inst_ser2par/id
   dr_q2 pin CLK0 (INVERTED) must match programming for block
   data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[6].inst_ser2par/in
   st_delay pin IOCLK0 (NOT INVERTED) when using a shared clock inversion
   source.
ERROR:PhysDesignRules:2003 - Unsupported clocking structure. Inversion
   programming for block
   data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[6].inst_ser2par/id
   dr_q2 pin CLK1 (NOT INVERTED) must match programming for block
   data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[6].inst_ser2par/in
   st_delay pin IOCLK1 (INVERTED) when using a shared clock inversion source.
ERROR:PhysDesignRules:2003 - Unsupported clocking structure. Inversion
   programming for block
   data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[7].inst_ser2par/id
   dr_q2 pin CLK0 (INVERTED) must match programming for block
   data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[7].inst_ser2par/in
   st_delay pin IOCLK0 (NOT INVERTED) when using a shared clock inversion
   source.
ERROR:PhysDesignRules:2003 - Unsupported clocking structure. Inversion
   programming for block
   data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[7].inst_ser2par/id
   dr_q2 pin CLK1 (NOT INVERTED) must match programming for block
   data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[7].inst_ser2par/in
   st_delay pin IOCLK1 (INVERTED) when using a shared clock inversion source.
ERROR:PhysDesignRules:2003 - Unsupported clocking structure. Inversion
   programming for block
   data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[8].inst_ser2par/id
   dr_q2 pin CLK0 (INVERTED) must match programming for block
   data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[8].inst_ser2par/in
   st_delay pin IOCLK0 (NOT INVERTED) when using a shared clock inversion
   source.
ERROR:PhysDesignRules:2003 - Unsupported clocking structure. Inversion
   programming for block
   data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[8].inst_ser2par/id
   dr_q2 pin CLK1 (NOT INVERTED) must match programming for block
   data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[8].inst_ser2par/in
   st_delay pin IOCLK1 (INVERTED) when using a shared clock inversion source.
ERROR:PhysDesignRules:2003 - Unsupported clocking structure. Inversion
   programming for block
   data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[10].inst_ser2par/i
   ddr_q2 pin CLK0 (INVERTED) must match programming for block
   data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[10].inst_ser2par/i
   nst_delay pin IOCLK0 (NOT INVERTED) when using a shared clock inversion
   source.
ERROR:PhysDesignRules:2003 - Unsupported clocking structure. Inversion
   programming for block
   data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[10].inst_ser2par/i
   ddr_q2 pin CLK1 (NOT INVERTED) must match programming for block
   data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[10].inst_ser2par/i
   nst_delay pin IOCLK1 (INVERTED) when using a shared clock inversion source.
ERROR:PhysDesignRules:2003 - Unsupported clocking structure. Inversion
   programming for block
   data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[11].inst_ser2par/i
   ddr_q2 pin CLK0 (INVERTED) must match programming for block
   data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[11].inst_ser2par/i
   nst_delay pin IOCLK0 (NOT INVERTED) when using a shared clock inversion
   source.
ERROR:PhysDesignRules:2003 - Unsupported clocking structure. Inversion
   programming for block
   data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[11].inst_ser2par/i
   ddr_q2 pin CLK1 (NOT INVERTED) must match programming for block
   data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[11].inst_ser2par/i
   nst_delay pin IOCLK1 (INVERTED) when using a shared clock inversion source.
ERROR:PhysDesignRules:2003 - Unsupported clocking structure. Inversion
   programming for block
   data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[12].inst_ser2par/i
   ddr_q2 pin CLK0 (INVERTED) must match programming for block
   data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[12].inst_ser2par/i
   nst_delay pin IOCLK0 (NOT INVERTED) when using a shared clock inversion
   source.
ERROR:PhysDesignRules:2003 - Unsupported clocking structure. Inversion
   programming for block
   data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[12].inst_ser2par/i
   ddr_q2 pin CLK1 (NOT INVERTED) must match programming for block
   data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[12].inst_ser2par/i
   nst_delay pin IOCLK1 (INVERTED) when using a shared clock inversion source.
ERROR:PhysDesignRules:2003 - Unsupported clocking structure. Inversion
   programming for block
   data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[13].inst_ser2par/i
   ddr_q2 pin CLK0 (INVERTED) must match programming for block
   data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[13].inst_ser2par/i
   nst_delay pin IOCLK0 (NOT INVERTED) when using a shared clock inversion
   source.
ERROR:PhysDesignRules:2003 - Unsupported clocking structure. Inversion
   programming for block
   data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[13].inst_ser2par/i
   ddr_q2 pin CLK1 (NOT INVERTED) must match programming for block
   data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[13].inst_ser2par/i
   nst_delay pin IOCLK1 (INVERTED) when using a shared clock inversion source.
ERROR:PhysDesignRules:2003 - Unsupported clocking structure. Inversion
   programming for block
   data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[14].inst_ser2par/i
   ddr_q2 pin CLK0 (INVERTED) must match programming for block
   data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[14].inst_ser2par/i
   nst_delay pin IOCLK0 (NOT INVERTED) when using a shared clock inversion
   source.
ERROR:PhysDesignRules:2003 - Unsupported clocking structure. Inversion
   programming for block
   data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[14].inst_ser2par/i
   ddr_q2 pin CLK1 (NOT INVERTED) must match programming for block
   data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[14].inst_ser2par/i
   nst_delay pin IOCLK1 (INVERTED) when using a shared clock inversion source.
ERROR:PhysDesignRules:2003 - Unsupported clocking structure. Inversion
   programming for block
   data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[15].inst_ser2par/i
   ddr_q2 pin CLK0 (INVERTED) must match programming for block
   data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[15].inst_ser2par/i
   nst_delay pin IOCLK0 (NOT INVERTED) when using a shared clock inversion
   source.
ERROR:PhysDesignRules:2003 - Unsupported clocking structure. Inversion
   programming for block
   data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[15].inst_ser2par/i
   ddr_q2 pin CLK1 (NOT INVERTED) must match programming for block
   data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[15].inst_ser2par/i
   nst_delay pin IOCLK1 (INVERTED) when using a shared clock inversion source.
ERROR:Bitgen:25 - DRC detected 64 errors and 0 warnings.  Please see the
   previously displayed individual error or warning messages for more details.

 

 

There some weird problems with the clock inputs to IDDR2 and IODELAY2.

 

In my design i generated two clocks : serial and parallel and i'm clocking IODELAY and IDDR with only clk_ser, code looks like this: 

 

  clk_ser_inv <= not clk_ser;
  
  -------------------------------------------------
  --   64-TAP DELAY: IODELAY2 PRIMITIVE          --
  -------------------------------------------------
  inst_delay : iodelay2
    generic map (
      IDELAY_TYPE  => "VARIABLE_FROM_ZERO",
      DATA_RATE    => "DDR",
      IDELAY_VALUE => 0
      )
    port map (
      busy     => open,
      cal      => '0',
      ce       => dly_ce,
      clk      => clk_ser,
      dataout  => data_ser_del,
      dataout2 => open,
      dout     => open,
      idatain  => data_ser,
      inc      => '1',
      ioclk0   => clk_ser,
      ioclk1   => clk_ser_inv,
      odatain  => '1',
      rst      => dly_rst,
      t        => '1',
      tout     => open
      );

  -------------------------------------------------
  --   DDR INPUT FLIPFLOPS: IDDR PRIMITIVE       --
  -------------------------------------------------
  inst_iddr : iddr2
    generic map (
      DDR_ALIGNMENT => "C0",
      INIT_Q0       => '0',
      INIT_Q1       => '0',
      SRTYPE        => "SYNC"
      )
    port map (
      d  => data_ser_del,
      c0 => clk_ser_inv,
      c1 => clk_ser,
      ce => '1',
      r  => '0',
      s  => '0',
      q0 => iddr_q1,
      q1 => iddr_q2
      );

 

I'm connecting pure clk_ser to IOCLK0's inputs of IODELAY2 and IDDR2, and inverted version of this clock to IOCLK1's ports of those primitives.

 

I'm also using clk ser to connect to CLK input port of the IODELAY2.

 

Some of this causes PhusDesignRules to be broken, but which one?

 

I'm attaching a NCD file if anyone is interested in finding out what wrong with this design 

 

 

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Xilinx Employee
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This error is because you are not using the same CLK0 for both the IDELAY2 and the ILOGIC.  They must both be the same phase.  Using different phases for these 2 components will not work. 

 

ERROR:PhysDesignRules:2003 - Unsupported clocking structure. Inversion programming for block
   data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[0].inst_ser2par/iddr_q2 pin CLK0 (INVERTED) must match programming for block data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[0].inst_ser2par/inst_delay pin IOCLK0 (NOT INVERTED) when using a shared clock inversion source.

 

Your IODELAY2 has

    ioclk0   => clk_ser,
    ioclk1   => clk_ser_inv,

 

and your IDDR has

    c0 => clk_ser_inv,
    c1 => clk_ser,

 

The IOCLK0 and the C0 Clock must be the same phase or they will count as 2 differnt clocks, essentially with this configuration you now have 4 clocks attempting to route into this IOB cell.   If you can fix this then we can look a the next error but this has to be fixed or you will not be able to implement this design in a Spartan-6 IOB.

 

 

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Registered: ‎12-21-2011

Ok,  i got rid of this particular error, by connecting clocks in manner described below:

 

  clk_ser_inv <= not clk_ser;
  
  -------------------------------------------------
  --   64-TAP DELAY: IODELAY2 PRIMITIVE          --
  -------------------------------------------------
  inst_delay : iodelay2
    generic map (
      IDELAY_TYPE  => "VARIABLE_FROM_ZERO",
      DATA_RATE    => "DDR",
      IDELAY_VALUE => 0
      )
    port map (
      busy     => open,
      cal      => '0',
      ce       => dly_ce,
      clk      => clk_ser,
      dataout  => data_ser_del,
      dataout2 => open,
      dout     => open,
      idatain  => data_ser,
      inc      => '1',
      ioclk0   => clk_ser,
      ioclk1   => clk_ser_inv,
      odatain  => '1',
      rst      => dly_rst,
      t        => '1',
      tout     => open
      );

  -------------------------------------------------
  --   DDR INPUT FLIPFLOPS: IDDR PRIMITIVE       --
  -------------------------------------------------
  inst_iddr : iddr2
    generic map (
      DDR_ALIGNMENT => "C0",
      INIT_Q0       => '0',
      INIT_Q1       => '0',
      SRTYPE        => "SYNC"
      )
    port map (
      d  => data_ser_del,
      c0 => clk_ser,
      c1 => clk_ser_inv,
      ce => '1',
      r  => '0',
      s  => '0',
      q0 => iddr_q1,
      q1 => iddr_q2
      );

 

ERROR:PhysDesignRules:2003 disappeared, but there are some left and i really don't understand what to do to fix them.

 

 

Started : "Generate Programming File".
Running bitgen...
Command Line: bitgen -intstyle ise -f m_k40_top.ut m_k40_top.ncd
ERROR:PhysDesignRules:1765 - Issue with pin connections and/or configuration on
   block:<data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[8].inst_ser
   2par/inst_delay>:<IODELAY2_IODELAY2>.  For DELAY_SRC IO programming the T
   input pin of IODELAY2 must be connected.
ERROR:PhysDesignRules:1768 - Issue with pin connections and/or configuration on
   block:<data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[8].inst_ser
   2par/inst_delay>:<IODELAY2_IODELAY2>.  For DELAY_SRC programming ODATAIN or
   IO the ODATAIN input pin of IODELAY2 must be connected.
ERROR:PhysDesignRules:1765 - Issue with pin connections and/or configuration on
   block:<data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[10].inst_se
   r2par/inst_delay>:<IODELAY2_IODELAY2>.  For DELAY_SRC IO programming the T
   input pin of IODELAY2 must be connected.
ERROR:PhysDesignRules:1768 - Issue with pin connections and/or configuration on
   block:<data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[10].inst_se
   r2par/inst_delay>:<IODELAY2_IODELAY2>.  For DELAY_SRC programming ODATAIN or
   IO the ODATAIN input pin of IODELAY2 must be connected.
ERROR:PhysDesignRules:1765 - Issue with pin connections and/or configuration on
   block:<data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[9].inst_ser
   2par/inst_delay>:<IODELAY2_IODELAY2>.  For DELAY_SRC IO programming the T
   input pin of IODELAY2 must be connected.
ERROR:PhysDesignRules:1768 - Issue with pin connections and/or configuration on
   block:<data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[9].inst_ser
   2par/inst_delay>:<IODELAY2_IODELAY2>.  For DELAY_SRC programming ODATAIN or
   IO the ODATAIN input pin of IODELAY2 must be connected.
ERROR:PhysDesignRules:1765 - Issue with pin connections and/or configuration on
   block:<data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[11].inst_se
   r2par/inst_delay>:<IODELAY2_IODELAY2>.  For DELAY_SRC IO programming the T
   input pin of IODELAY2 must be connected.
ERROR:PhysDesignRules:1768 - Issue with pin connections and/or configuration on
   block:<data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[11].inst_se
   r2par/inst_delay>:<IODELAY2_IODELAY2>.  For DELAY_SRC programming ODATAIN or
   IO the ODATAIN input pin of IODELAY2 must be connected.
ERROR:PhysDesignRules:1765 - Issue with pin connections and/or configuration on
   block:<data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[0].inst_ser
   2par/inst_delay>:<IODELAY2_IODELAY2>.  For DELAY_SRC IO programming the T
   input pin of IODELAY2 must be connected.
ERROR:PhysDesignRules:1768 - Issue with pin connections and/or configuration on
   block:<data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[0].inst_ser
   2par/inst_delay>:<IODELAY2_IODELAY2>.  For DELAY_SRC programming ODATAIN or
   IO the ODATAIN input pin of IODELAY2 must be connected.
ERROR:PhysDesignRules:1765 - Issue with pin connections and/or configuration on
   block:<data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[12].inst_se
   r2par/inst_delay>:<IODELAY2_IODELAY2>.  For DELAY_SRC IO programming the T
   input pin of IODELAY2 must be connected.
ERROR:PhysDesignRules:1768 - Issue with pin connections and/or configuration on
   block:<data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[12].inst_se
   r2par/inst_delay>:<IODELAY2_IODELAY2>.  For DELAY_SRC programming ODATAIN or
   IO the ODATAIN input pin of IODELAY2 must be connected.
ERROR:PhysDesignRules:1765 - Issue with pin connections and/or configuration on
   block:<data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[1].inst_ser
   2par/inst_delay>:<IODELAY2_IODELAY2>.  For DELAY_SRC IO programming the T
   input pin of IODELAY2 must be connected.
ERROR:PhysDesignRules:1768 - Issue with pin connections and/or configuration on
   block:<data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[1].inst_ser
   2par/inst_delay>:<IODELAY2_IODELAY2>.  For DELAY_SRC programming ODATAIN or
   IO the ODATAIN input pin of IODELAY2 must be connected.
ERROR:PhysDesignRules:1765 - Issue with pin connections and/or configuration on
   block:<data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[13].inst_se
   r2par/inst_delay>:<IODELAY2_IODELAY2>.  For DELAY_SRC IO programming the T
   input pin of IODELAY2 must be connected.
ERROR:PhysDesignRules:1768 - Issue with pin connections and/or configuration on
   block:<data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[13].inst_se
   r2par/inst_delay>:<IODELAY2_IODELAY2>.  For DELAY_SRC programming ODATAIN or
   IO the ODATAIN input pin of IODELAY2 must be connected.
ERROR:PhysDesignRules:1765 - Issue with pin connections and/or configuration on
   block:<data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[2].inst_ser
   2par/inst_delay>:<IODELAY2_IODELAY2>.  For DELAY_SRC IO programming the T
   input pin of IODELAY2 must be connected.
ERROR:PhysDesignRules:1768 - Issue with pin connections and/or configuration on
   block:<data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[2].inst_ser
   2par/inst_delay>:<IODELAY2_IODELAY2>.  For DELAY_SRC programming ODATAIN or
   IO the ODATAIN input pin of IODELAY2 must be connected.
ERROR:PhysDesignRules:1765 - Issue with pin connections and/or configuration on
   block:<data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[14].inst_se
   r2par/inst_delay>:<IODELAY2_IODELAY2>.  For DELAY_SRC IO programming the T
   input pin of IODELAY2 must be connected.
ERROR:PhysDesignRules:1768 - Issue with pin connections and/or configuration on
   block:<data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[14].inst_se
   r2par/inst_delay>:<IODELAY2_IODELAY2>.  For DELAY_SRC programming ODATAIN or
   IO the ODATAIN input pin of IODELAY2 must be connected.
ERROR:PhysDesignRules:1765 - Issue with pin connections and/or configuration on
   block:<data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[3].inst_ser
   2par/inst_delay>:<IODELAY2_IODELAY2>.  For DELAY_SRC IO programming the T
   input pin of IODELAY2 must be connected.
ERROR:PhysDesignRules:1768 - Issue with pin connections and/or configuration on
   block:<data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[3].inst_ser
   2par/inst_delay>:<IODELAY2_IODELAY2>.  For DELAY_SRC programming ODATAIN or
   IO the ODATAIN input pin of IODELAY2 must be connected.
ERROR:PhysDesignRules:1765 - Issue with pin connections and/or configuration on
   block:<data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[15].inst_se
   r2par/inst_delay>:<IODELAY2_IODELAY2>.  For DELAY_SRC IO programming the T
   input pin of IODELAY2 must be connected.
ERROR:PhysDesignRules:1768 - Issue with pin connections and/or configuration on
   block:<data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[15].inst_se
   r2par/inst_delay>:<IODELAY2_IODELAY2>.  For DELAY_SRC programming ODATAIN or
   IO the ODATAIN input pin of IODELAY2 must be connected.
ERROR:PhysDesignRules:1765 - Issue with pin connections and/or configuration on
   block:<data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[4].inst_ser
   2par/inst_delay>:<IODELAY2_IODELAY2>.  For DELAY_SRC IO programming the T
   input pin of IODELAY2 must be connected.
ERROR:PhysDesignRules:1768 - Issue with pin connections and/or configuration on
   block:<data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[4].inst_ser
   2par/inst_delay>:<IODELAY2_IODELAY2>.  For DELAY_SRC programming ODATAIN or
   IO the ODATAIN input pin of IODELAY2 must be connected.
ERROR:PhysDesignRules:1765 - Issue with pin connections and/or configuration on
   block:<data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[5].inst_ser
   2par/inst_delay>:<IODELAY2_IODELAY2>.  For DELAY_SRC IO programming the T
   input pin of IODELAY2 must be connected.
ERROR:PhysDesignRules:1768 - Issue with pin connections and/or configuration on
   block:<data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[5].inst_ser
   2par/inst_delay>:<IODELAY2_IODELAY2>.  For DELAY_SRC programming ODATAIN or
   IO the ODATAIN input pin of IODELAY2 must be connected.
ERROR:PhysDesignRules:1765 - Issue with pin connections and/or configuration on
   block:<data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[6].inst_ser
   2par/inst_delay>:<IODELAY2_IODELAY2>.  For DELAY_SRC IO programming the T
   input pin of IODELAY2 must be connected.
ERROR:PhysDesignRules:1768 - Issue with pin connections and/or configuration on
   block:<data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[6].inst_ser
   2par/inst_delay>:<IODELAY2_IODELAY2>.  For DELAY_SRC programming ODATAIN or
   IO the ODATAIN input pin of IODELAY2 must be connected.
ERROR:PhysDesignRules:1765 - Issue with pin connections and/or configuration on
   block:<data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[7].inst_ser
   2par/inst_delay>:<IODELAY2_IODELAY2>.  For DELAY_SRC IO programming the T
   input pin of IODELAY2 must be connected.
ERROR:PhysDesignRules:1768 - Issue with pin connections and/or configuration on
   block:<data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[7].inst_ser
   2par/inst_delay>:<IODELAY2_IODELAY2>.  For DELAY_SRC programming ODATAIN or
   IO the ODATAIN input pin of IODELAY2 must be connected.
ERROR:Bitgen:25 - DRC detected 32 errors and 0 warnings.  Please see the
   previously displayed individual error or warning messages for more details.

 

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Xilinx Employee
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Someone else will need to chime in if they see an issu with your configuration.  My comments are based on place and routing. Though the error is saying that you have set the DELAY_SRC to ODATIN or IO (likely IO after reading both messages).  Maybe you should set it specificaylly to IDATAIN and see if that works around the confusion. I do not see where you have set it in your HDL.

 

This error says you have delay_src to be IO.

 

ERROR:PhysDesignRules:1765 - Issue with pin connections and/or configuration on block:

<data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[8].inst_ser2par/inst_delay>:<IODELAY2_IODELAY2>.  For DELAY_SRC IO programming the T input pin of IODELAY2 must be connected. 

 

 

The next error then basically is saying the same thing.

 

ERROR:PhysDesignRules:1768 - Issue with pin connections and/or configuration on block:

<data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[8].inst_ser2par/inst_delay>:<IODELAY2_IODELAY2>.  For DELAY_SRC programming ODATAIN or IO the ODATAIN input pin of IODELAY2 must be connected.

 

View solution in original post

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Registered: ‎12-21-2011

It finally worked, thank you so much:D

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