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Observer nilnullzip
Observer
740 Views
Registered: ‎09-19-2018

Unusual net delay and: [Designutils 20-756] Invalid physical equation for the C6LUT

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I have encountered an unusually high delay on a very short single fanout net. See screen shot. The source and destinations are very close. When I run phys_opt_design on the checkpoint, it reports multiple [Designutils 20-756] errors that I think might be related. See below.

 Can this long delay be correct? Any suggestions for how to force this path to be rerouted, and possibly redone? I tried "route_design -tns_cleanup" and that showed no change.

 

Screen Shot 2018-12-30 at 8.52.52 AM.png

 

CRITICAL WARNING: [Designutils 20-756] Invalid physical equation for the C6LUT bel in site SLICE_X95Y203. The original INIT is 'AFA0CFCFAFA0C0C0'. The logical cell is 'WRAPPER_INST/CL/ms_periph_inst/rb/rdata[8]_INST_0_i_11'. Reason: The bit width of the INIT value does not match the number of used input pins '5'. Please verify that all required logical pins are used for this cell.
Bel 9: element name: 'C6LUT'
Attr: 'C_I_USED' Value: NOT CONFIGURED
Attr: 'LUTMODE' Value: LUT
Attr: 'LUTRAMMODE' Value: SPRAM32
Attr: 'WA7_USED' Value: NOT CONFIGURED
Attr: 'WA8_USED' Value: NOT CONFIGURED
Attr: 'WA9_USED' Value: NOT CONFIGURED
Attr: 'EQN' Value: 64'hAFA0CFCFAFA0C0C0
Pin : index 0: A1 : Logical net: 'rdata[8]_INST_0_i_15_n_0'
Pin : index 1: A2 : Logical net: 'ms_raddr[3]'
Pin : index 3: A4 : Logical net: 'rdata[30]_INST_0_i_24_n_0'
Pin : index 4: A5 : Logical net: 'ms_raddr[2]'
Pin : index 5: A6 : Logical net: 'rdata[30]_INST_0_i_23_n_0'
Pin : index 21: O6 : Logical net: 'rdata[8]_INST_0_i_11_n_0'
Inst: 'rdata[8]_INST_0_i_11'
CellType: 'LUT6'
Pin Swappable:
Inst term 'I5' ('I5') -> Bel pin 'A1' (by placer)
Inst term 'I2' ('I2') -> Bel pin 'A2' (by placer)
Not assigned -> Bel pin 'A3'
Inst term 'I3' ('I3') -> Bel pin 'A4' (by placer)
Inst term 'I4' ('I4') -> Bel pin 'A5' (by placer)
Inst term 'I1' ('I1') -> Bel pin 'A6' (by placer)

 

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Xilinx Employee
Xilinx Employee
670 Views
Registered: ‎05-08-2012

Re: Unusual net delay and: [Designutils 20-756] Invalid physical equation for the C6LUT

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Hi @nilnullzip. I would suggest checking the hold requirement on this path. i would only expect such a long delay if the router is trying to meet a large hold requirement.

report_timing -from [get_pins <from_pin>] -to [get_pins <to_pin>] -hold

For the Designutils 20-756 warning, I would check the physical connectivity after implementation from the device view. Are only 5 pins used with the INIT value for the LUT using 6 inputs? This is what the message is detailing. Going back and comparing the logical and physical connectivity at different points of the flow (opt_design, place_design, phys_opt_design...) could help to understand how this has happened.


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4 Replies
Xilinx Employee
Xilinx Employee
671 Views
Registered: ‎05-08-2012

Re: Unusual net delay and: [Designutils 20-756] Invalid physical equation for the C6LUT

Jump to solution

Hi @nilnullzip. I would suggest checking the hold requirement on this path. i would only expect such a long delay if the router is trying to meet a large hold requirement.

report_timing -from [get_pins <from_pin>] -to [get_pins <to_pin>] -hold

For the Designutils 20-756 warning, I would check the physical connectivity after implementation from the device view. Are only 5 pins used with the INIT value for the LUT using 6 inputs? This is what the message is detailing. Going back and comparing the logical and physical connectivity at different points of the flow (opt_design, place_design, phys_opt_design...) could help to understand how this has happened.


-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

---------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
---------------------------------------------------------------------------------------------
Historian
Historian
665 Views
Registered: ‎01-23-2009

Re: Unusual net delay and: [Designutils 20-756] Invalid physical equation for the C6LUT

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I agree with @marcb - long net delays when the fanout is one and the cells are very close to each other (as they are here) are tell-tale signs that the tool is trying to fix hold times.

Since the net delays are really large, there is a good likelihood that this is "incorrect" hold time fixing, coming from an illegal clock crossing or other illegal clock structure - if your clocks are managed properly, you should never have "large" hold times to fix.

So you need to show us the comple path - specifically the clocking sections. From those it should be obvious as to what is wrong with your clocking which creates this incorrect hold time fixing.

Avrum

Observer nilnullzip
Observer
656 Views
Registered: ‎09-19-2018

Re: Unusual net delay and: [Designutils 20-756] Invalid physical equation for the C6LUT

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Thank you for that insight. I think perhaps this was a hold time issue. The router was showing very high hold times, so I rearranged my clocking and the hold times improved and this error went away. See below the current report with WHS=-1.320 and TNS=86.674. Do you think this is too much?

I'm still having other problems. The router is giving up saying "failed to resolve global congestion". However all the congestion metrics don't seem to show a problem. So I'm thinking something else is up and the router messages are not pointing to the cause.

 

Phase 2.4 Update Timing
Phase 2.4 Update Timing | Checksum: cc27b88d

Time (s): cpu = 00:43:13 ; elapsed = 00:17:38 . Memory (MB): peak = 23924.797 ; gain = 0.000 ; free physical = 22538 ; free virtual = 78328
INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.017 | TNS=0.000 | WHS=-1.320 | THS=-86.674|

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Historian
Historian
647 Views
Registered: ‎01-23-2009

Re: Unusual net delay and: [Designutils 20-756] Invalid physical equation for the C6LUT

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WHS=-1.320 and TNS=86.674. Do you think this is too much?

WAY too much.

Hold time issues are caused by clock skew. Normal clock skews would be in the range of 200ps or maybe a little more. If there is any path that has a hold time requirement that is more than 300ps, then you have a clock problem - you have a clock crossing between clock domains that are not properly synchronized or phase matched. This will cause the tool to try and fix the hold times by adding tons of extra routing (to delay the signals to try and meet the hold time requirement), which can, in turn, result in routing congestion.

You need to carefully revisit all your clocks and your clock crossings. Something is wrong with your design if you are getting hold time violations over 1ns (and this is presumably after the tool has already started trying to fix them).

Avrum