UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Observer malharjere
Observer
1,210 Views
Registered: ‎12-11-2017

Uploading file to FPGA

I have a Kintex KC705 FPGA with Vivado 2017.4 connected to my PC using a USB-UART cable. I want to upload a .txt file to the FPGA and specifically create a memory region where all the bits of the file are stored, and inspect these bits to see that they match the .txt file. Are there any guides or tutorials to go about doing this, or could anyone shed some light on this? Thanks.

0 Kudos
5 Replies
Xilinx Employee
Xilinx Employee
1,153 Views
Registered: ‎09-22-2015

Re: Uploading file to FPGA

HI @malharjere,

              You need USB-JTAG to transfer any data to FPGA. Can you provide some more information about what you are trying to do by writing txt files to FPGA?

------------------------------------------------------------------------------------------------------------------------
Please mark an answer "Accept as solution" if a post has the solution to your issue.
------------------------------------------------------------------------------------------------------------------------
0 Kudos
Observer malharjere
Observer
1,148 Views
Registered: ‎12-11-2017

Re: Uploading file to FPGA

My end goal is to be able to broadcast the file over the GPIO SMA ports. My design approach is:

- Upload a file to the FPGA from my computer, where a ROM is created that stores the bits of the uploaded file

- Connect this memory to pin Y23 and send out each bit triggered on a clock in the form of a physical signal

0 Kudos
Xilinx Employee
Xilinx Employee
1,105 Views
Registered: ‎09-22-2015

Re: Uploading file to FPGA

Hi @malharjere

This answer record provides steps to initialize BRAM with text value. This will be fixed to the bitstream and you cannot change values during runtime. If that is what is required, you should be able to set values using xdc file.

 

https://www.xilinx.com/support/answers/61387.html

 

For parsing the text file into these xdc commands, you will need to use tcl script commands.please read the following document regarding constraints and tcl:

http://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug903-vivado-using-constraints.pdf

http://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug835-vivado-tcl-commands.pdf

 

Another way would be to instantiate a Microblaze in your design and read the txt file and write to GPIO port using the C-language file IO an standalone driver GPIO IO constructs. If you are going with Microblaze, please open the Microblaze Example design in Vivado and follow steps provided here:
http://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug940-vivado-tutorial-embedded-design.pdf

 

 

 

------------------------------------------------------------------------------------------------------------------------
Please mark an answer "Accept as solution" if a post has the solution to your issue.
------------------------------------------------------------------------------------------------------------------------
0 Kudos
Observer malharjere
Observer
1,099 Views
Registered: ‎12-11-2017

Re: Uploading file to FPGA

GPIO through the MicroBlaze is too slow, I want a dedicated hardware module for it in Verilog instead. I found out in the simulation tool how to load the bits in memory and send them out at each positive clock edge, and I need to now generate that physical clock on my FPGA. How would I do this?

0 Kudos
Xilinx Employee
Xilinx Employee
1,096 Views
Registered: ‎09-22-2015

Re: Uploading file to FPGA

You should be able to get more info about generating clocks from this page of the above document:
https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug903-vivado-using-constraints.pdf#page=78

 

------------------------------------------------------------------------------------------------------------------------
Please mark an answer "Accept as solution" if a post has the solution to your issue.
------------------------------------------------------------------------------------------------------------------------
0 Kudos