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user@moduleus
Contributor
Contributor
1,633 Views
Registered: ‎12-05-2017

Using true differential ports as block design single-ended ports

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Hi,

 

I have to do a big design with lot of differiential ios and I would like to know how to convert differiential signals to single ended signals ONLY USING XDC TCL COMMANDS.

 

I want to have my block design with 1 port for each pair of differential signals. Then, using corrected xdc commands, I want that Vivado infers IBUFDS/OBUFDS without the need to code them into my hdl code
(
e.g.:

  IBUFDS_inst : IBUFDS
  generic map (
    DIFF_TERM => FALSE, -- Differential Termination
    IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
    IOSTANDARD => "DEFAULT")
  port map (
    O => ibufds_o(n), -- Buffer output
    I => ibufds_ip(n), -- Diff_p buffer input (connect directly to top-level port)
    IB => ibufds_in(n) -- Diff_n buffer input (connect directly to top-level port)
  );
).

 

I have seen that it is possible:
https://www.xilinx.com/support/answers/57109.html

But, I don't figure out HOW to do that using Vivado 2018.2.2.

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shameera
Moderator
Moderator
1,612 Views
Registered: ‎05-31-2017

Hi user@moduleus,

 

Vivado will not infer IBUFDS/OBUFDS. They have to be manually instantiated in the HDL.

Please check page 313 of UG953 for 7 series and page 278 of UG974 for Ultrascale regarding the same for IBUFDS.

View solution in original post

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shameera
Moderator
Moderator
1,613 Views
Registered: ‎05-31-2017

Hi user@moduleus,

 

Vivado will not infer IBUFDS/OBUFDS. They have to be manually instantiated in the HDL.

Please check page 313 of UG953 for 7 series and page 278 of UG974 for Ultrascale regarding the same for IBUFDS.

View solution in original post

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