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Anonymous
Not applicable
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VC707 BIST Implementation problems

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I have installed Vivado 2014.1 and downloaded the BIST example project( rdf0195-vc707-bist-c-2014-1.zip)  for the VC707. 

I re-synthesis  and re-implementation the BIST project to re-generate the bitstream file.  The resuts of the synthesis are the same  as the example's, but the implemetation results are different from the example's.  There is one critical warning in the implemetation results.

 

I have  re-synthesis  and re-implementation the BIST project many times , but the critical warning is still existing.

 

I want to know how can this happen, and how can I solve it?

 

I attached the picture of the resut.

 

My Os:  Win7   64bit

 

Thanks !

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result1.png
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Anonymous
Not applicable
14,355 Views

Hi,

 

  I found a new  situation.

 

  If I just re-implementation the BIST example,  the result is same as the example's.

 

  If I  re-synthesis the BIST example firstly, and then re-implementation it , there will be a critical warning.

 

  I hope this can help.

 

   regards, shuai 

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vijayak
Xilinx Employee
Xilinx Employee
9,183 Views
Registered: ‎10-24-2013
Hi,
Can you please give us the critical warning you are seeing?
Thanks,Vijay
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Anonymous
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Hi,

 

Critical warning information:

[Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations.

 

I attached the the timing summary report.

 

You can see the setup time violation information from the last attched file.

 

 

 I did some BIST implementation testings on two different computers again.

  The results are following:

 

(1)  OS:    Win7  32bit 

     CPU:   Intel(R) Core(TM) i3-3220 @ 3.30GHz

     RAM:   4.00GB

 

    The successful rate of implementation is less than 10%

 

 

 (2)   OS:   Win7  64bit

     CPU:   Intel(R) Core(TM) i7-3770 @ 3.50GHz

     RAM:   16.00GB

 

     The successful rate of implementation is about 50%.

 

 I want to know if your implementation can succeed every time.

 If yes, could you tell me how can I get my implementation successful every time? Is it related to the configuration of my computer? What is your computer configuration?

 

If no, could you explain me this situation? And how can I improve the successful rate of implementation?

 

Thanks!

Shuai

 

 

 

 

 

 

 

 

 

 

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Anonymous
Not applicable
14,356 Views

Hi,

 

  I found a new  situation.

 

  If I just re-implementation the BIST example,  the result is same as the example's.

 

  If I  re-synthesis the BIST example firstly, and then re-implementation it , there will be a critical warning.

 

  I hope this can help.

 

   regards, shuai 

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vijayak
Xilinx Employee
Xilinx Employee
9,120 Views
Registered: ‎10-24-2013
Hi,
Thanks for the solution. Please mark your post as solution.
Thanks,Vijay
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smarell
Community Manager
Community Manager
9,111 Views
Registered: ‎07-23-2012
Hi,

Please make sure that the synthesis/implementation settings of the project match with the settings provided in the .bat files.

Having different settings can result in different netlists.

Regards,
Krishna
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Anonymous
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Hi,

 

      I checked.  They are same.

 

      Could you re-synthesis and re-imlementation the BIST example on your PC to help me check the problem?

 

       software:               Vivado 2014.1

       BIST example:     rdf0195-vc707-bist-c-2014-1.zip

 

                                     download address: http://tgoogle.xilinx.com/search?output=xml_no_dtd&ie=UTF-8&oe=UTF-8&client=support&proxystylesheet=support&site=Answers_Docs&filter=0&resultsView=category&tab=bk&num=200&sortBy=date&show_dynamic_navigation=1&sort=date%3AD%3AR%3Ad1&documentClass=Docu...

 

 

Best regards, shuai

 

 

 

 

 

 

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