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Visitor mgoubert
Registered: ‎11-03-2012

VHDL resource estimation, map reports much higer usage

'm estimating my resource usage by counting the number of flip flop i need for a componenet. For exame when i estimate it for ins_controldata (simple counter and some I/O), i a use of 32 flipflops. When i look at the detailed map report of this component, Section 13 - Utilization by Hierarchy, i see that my estimations is close to the slice registers used for this component. Every slice has 4 Luts and 8 flipflops.

Now when i do the same for my finite state machine, inst_xtm640, i estimate my flipflop usage around 43 (including the 3 flipflops needed for the 6 states). When i look at the map report, i see my estimation is more or less correct (+-10% error). But the number of slices needed are much higer the the slice register and luts needed. It's 40 when if you look at the used luts, it should only be around 20.

Why are extra slices used for this component? Is it for speed optimization ?



| Module               | Partition | Slices*       | Slice Reg     | LUTs          |                                                            
| ++inst_controldata   |           | 6/6           | 35/35         | 20/20         |
| +++inst_xtm640       |           | 40/40         | 57/57         | 88/88         |
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2 Replies
Teacher rcingham
Registered: ‎09-09-2010

Re: VHDL resource estimation, map reports much higer usage

Which device?
What version of which tools?

"If it don't work in simulation, it won't work on the board."
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Xilinx Employee
Xilinx Employee
Registered: ‎07-01-2008

Re: VHDL resource estimation, map reports much higer usage

There is no reason the tools should minimize slice utilization. routability and timing goals are the priorities.

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