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Newbie djezenkuir
Newbie
379 Views
Registered: ‎05-07-2018

VIVADO infer more DSP than available in FPGA(vu9p)

Hello!

Our design has a lot of MACC construction, more thar available in vu9p. I expect that vivado infer DSP blocks as more as available in FPGA and other synth with LUT. But vivado infer more DSP block than available in fpga. I try different synthesys strategy, but nothing help...  

I don't use keep_hierarchy and use_dsp directive. I design MACC according to recomended teamplate.

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6 Replies
Scholar drjohnsmith
Scholar
362 Views
Registered: ‎07-09-2009

Re: VIVADO infer more DSP than available in FPGA(vu9p)

Whats the MACC template your using, is it inferring or instantating a DSP ?

How far out are you on DSP's ?

      a DSP is equivilent to a lot of LUT's ,

             just check you have th espace even in LUTs .

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Newbie djezenkuir
Newbie
353 Views
Registered: ‎05-07-2018

Re: VIVADO infer more DSP than available in FPGA(vu9p)

I want 16k macc. There is 6840 DSP and 1.2M LUT in vu9p.

Vivado infer ~8600DSP and 700K LUT... There is 500K of free LUTs!

I use out_of_context mode - only design with macc and no IP, IO, etc

Some addition after few experiments:

Generaly i use macc template with mux at output - DSP infer with mode C+(0 or (A2*B'')') and i have described situation.

Then i use pure MACC without mux - DSP infer with mode C+(A2*B) - and !!! VIVADO infer 6840(max available) and 850K LUTs.

P.S.: in both cases vivado infer 1 DSP for macc construction

Synth option is equal.

I want to use DSP with mux... Why behave of vivado is so strange?...

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Scholar drjohnsmith
Scholar
338 Views
Registered: ‎07-09-2009

Re: VIVADO infer more DSP than available in FPGA(vu9p)

don't suppose you can share the part of the code with the dsp in ?
<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
Newbie djezenkuir
Newbie
329 Views
Registered: ‎05-07-2018

Re: VIVADO infer more DSP than available in FPGA(vu9p)

This is extracted macc structure from my design

module for_share (
    input [   BITS-1:0] a        ,
    input [   BITS-1:0] b        ,
    input [PS_BITS-1:0] i_ps_data,
    output logic signed [PS_BITS-1:0]r_ps_data,
    input               i__bypass,

    input clk,
    input reset_x
);

logic signed [BITS-1:0] a_reg;
logic signed [BITS-1:0] b_reg;
logic signed [BITS*2-1:0] w_mult;
logic signed [PS_BITS-1:0]mult_reg;

    always_ff @(posedge clk ) begin
        if (reset_x == 1'b1) begin
            b_reg <= 'b0;
            a_reg <= 'b0;
        end
        else begin
            b_reg <= b;
            a_reg <= a;

        end
    end


    always_comb begin : mult
        w_mult = a_reg * b_reg;
    end

    always_ff @(posedge clk) begin
        mult_reg <= $signed(w_mult);
    end

    always_ff @(posedge clk) begin : macc_out_reg // mode_forward
        // if (i_pe_bypass == 1'b1)
        //     r_ps_data <= i_ps_data;
        // else
        `ifdef DSP_OUT_MUX
            r_ps_data <= !i__bypass ? {mult_reg + $signed(i_ps_data)} :  $signed(i_ps_data);
        `else
            r_ps_data <= mult_reg + $signed(i_ps_data);
        `endif
    end

endmodule
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Scholar dgisselq
Scholar
328 Views
Registered: ‎05-21-2015

Re: VIVADO infer more DSP than available in FPGA(vu9p)

@djezenkuir,

There are a couple of basic answers to this problem.  You can ...

  1. Adjust your logic to use something much smaller than 18x18 bit multiplies.  For example, a 4x4 bit multiply can easily be created from logic, without needing a DSP.
  2. You may find a simpler implementation of the same thing that doesn't use as many multiplies.  For example, if you are using a linear phase filter, you may be able to halve the number of multiplies.  If that's not enough, both Hilbert and halfband filters have a structure where every other coefficient is zero--that can halve your number of multiplies again
  3. Adjust your logic to share the multiplies between parts and pieces of your logic, as @drjohnsmith has suggested.  This really depends upon the requirements within your design.  For example, if you are running an N-tap filtering operation at fewer than one clock per output sample, you can share the multiplies across clock periods.  This also applies to symmetric (linear-phase) and Hilbert/halfband optimizations as well.
  4. Often times, you can cascade CIC filters with a downsampler and a slower filter to achieve the same effect, but for fewer multiplies.
  5. Sometimes you can buy a bigger FPGA.  In your example, this might be prohibitively expensive.
  6. Alternatively, you might be able to cascade the outputs from one FPGA board into another board

Hopefully one (or more) of these ideas might help.  I'll admit they are rather signal processing centric, but I'd wager there are other optimizations available for other problem domains as well.

Dan

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Newbie djezenkuir
Newbie
322 Views
Registered: ‎05-07-2018

Re: VIVADO infer more DSP than available in FPGA(vu9p)

Hello!

This is not an answer for my question!

vu9p has enough resourses for utilization my design. 16k MACC structure is a significant feature. It is not a filter... If out_mux isn't used in dsp everything is OK! 

Why vivado overutilize DSP if there are available LUT resourses? 

How can i make vivado use only available DSP? (synthesys_default with max_dsp directive don't help)

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