UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Newbie nealpalmer
Newbie
169 Views
Registered: ‎05-03-2010

VU13P 2018.3 "Inter-SLR connectivity check:" fails with 13% of SLR routing used?

I have a design that has previously gotten through 'write_bitstream' in vivado 2018.3.  I did some minor placement changes, and now it fails in 'write_bitstream' with the following errors:

ERROR: [DRC SLRC-1] Inter-SLR connectivity check: At least 29985 connections are required between SLR2 and SLR3 but only 23040 are available
ERROR: [DRC SLRC-1] Inter-SLR connectivity check: At least 59287 connections are required between SLR1 and SLR2 but only 23040 are available
ERROR: [DRC SLRC-1] Inter-SLR connectivity check: At least 85217 connections are required between SLR0 and SLR1 but only 23040 are available

report_utilization shows that a low percentage is actually used in the routing:

12. SLR Connectivity
--------------------

+----------------------------------+------+-------+-----------+-------+
| | Used | Fixed | Available | Util% |
+----------------------------------+------+-------+-----------+-------+
| SLR3 <-> SLR2 | 1747 | | 23040 | 7.58 |
| SLR2 -> SLR3 | 1198 | | | 5.20 |
| Using TX_REG only | 0 | 0 | | |
| Using RX_REG only | 0 | 0 | | |
| Using Both TX_REG and RX_REG | 0 | 0 | | |
| SLR3 -> SLR2 | 549 | | | 2.38 |
| Using TX_REG only | 0 | 0 | | |
| Using RX_REG only | 0 | 0 | | |
| Using Both TX_REG and RX_REG | 0 | 0 | | |
| SLR2 <-> SLR1 | 2836 | | 23040 | 12.31 |
| SLR1 -> SLR2 | 1214 | | | 5.27 |
| Using TX_REG only | 0 | 0 | | |
| Using RX_REG only | 0 | 0 | | |
| Using Both TX_REG and RX_REG | 0 | 0 | | |
| SLR2 -> SLR1 | 1622 | | | 7.04 |
| Using TX_REG only | 0 | 0 | | |
| Using RX_REG only | 0 | 0 | | |
| Using Both TX_REG and RX_REG | 0 | 0 | | |
| SLR1 <-> SLR0 | 448 | | 23040 | 1.94 |
| SLR0 -> SLR1 | 129 | | | 0.56 |
| Using TX_REG only | 0 | 0 | | |
| Using RX_REG only | 0 | 0 | | |
| Using Both TX_REG and RX_REG | 0 | 0 | | |
| SLR1 -> SLR0 | 319 | | | 1.38 |
| Using TX_REG only | 0 | 0 | | |
| Using RX_REG only | 0 | 0 | | |
| Using Both TX_REG and RX_REG | 0 | 0 | | |
+----------------------------------+------+-------+-----------+-------+
| Total SLLs Used | 5031 | | | |
+----------------------------------+------+-------+-----------+-------+


13. SLR Connectivity Matrix
---------------------------

+------+------+------+------+------+
| | SLR3 | SLR2 | SLR1 | SLR0 |
+------+------+------+------+------+
| SLR3 | 0 | 549 | 0 | 0 |
| SLR2 | 1198 | 0 | 1622 | 0 |
| SLR1 | 212 | 1214 | 0 | 319 |
| SLR0 | 83 | 83 | 129 | 0 |
+------+------+------+------+------+

Any idea why?

0 Kudos
2 Replies
Moderator
Moderator
58 Views
Registered: ‎01-16-2013

Re: VU13P 2018.3 "Inter-SLR connectivity check:" fails with 13% of SLR routing used?

@nealpalmer

 

If you have done some minor placement changes then try using incremental compilation feature in Vivado which might give good results with reduced runtime.

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_3/ug904-vivado-implementation.pdf#page=97

--Syed

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------
0 Kudos
Xilinx Employee
Xilinx Employee
29 Views
Registered: ‎03-29-2013

Re: VU13P 2018.3 "Inter-SLR connectivity check:" fails with 13% of SLR routing used?

Hi Neal,

Are you running report_utilization after the successful place_design or the failing one?

Did you change the synthesis settings?

-Fred

0 Kudos