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Registered: ‎07-09-2013

Valid FCVO value



I got the following error while compiling the ZC706 hardware:


[LIT 693] Block 'MMCME2_ADV symbol "system_i/axi_clkgen_0/axi_clkgen_0/USER_LOGIC_I/i_clkgen/i_mmcm"' has its target frequency, FVCO, out of range. Valid FVCO range varies depending on speed grade: 600MHz - 1200MHz(-1), 600MHz - 1440MHz(-2), 600MHz - 1600MHz(-3). The computed FCVO is a function of the input frequency CLKIN1_PERIOD, the division factor DIVCLK_DIVIDE, and the CLKFBOUT_MULT_F attribute (FVCO = 1000*CLKFBOUT_MULT_F/(CLKIN1_PERIOD*DIVCLK_DIVIDE)). The CLKIN_PERIOD attribute may have been set by ngdbuild based on the user specified PERIOD constraint. The current calculated FVCO is 222.727273 MHz.. However, I found that


    .DIVCLK_DIVIDE (11),
    .CLKFBOUT_MULT_F (49.000),
    .CLKFBOUT_PHASE (0.000),
    .CLKOUT0_DIVIDE_F (6.000),
    .CLKOUT0_PHASE (0.000),
    .CLKOUT0_DUTY_CYCLE (0.500),
    .CLKOUT1_DIVIDE (3),
    .CLKOUT1_PHASE (0.000),
    .CLKOUT1_DUTY_CYCLE (0.500),
    .CLKIN1_PERIOD (5.000),
    .REF_JITTER1 (0.010))
  i_mmcm (
    .CLKFBOUT (mmcm_fb_clk_s),
    .CLKFBIN (buf_fb_clk_s),
    .CLKFBOUTB (),
    .CLKOUT0 (mmcm_clk_s),
    .CLKOUT0B (),
    .CLKOUT1 (mmcm_clk_s1),
    .CLKOUT1B (),
    .CLKOUT2 (),
    .CLKOUT2B (),
    .CLKOUT3 (),
    .CLKOUT3B (),
    .CLKOUT4 (),
    .CLKOUT5 (),
    .CLKOUT6 (),
    .CLKIN1 (ref_clk),
    .CLKIN2 (1'b0),
    .CLKINSEL (1'b1),
    .DCLK (up_clk),
    .DADDR (mmcm_addr),
    .DEN (mmcm_sel),
    .DI (mmcm_wdata),
    .DO (mmcm_rdata_s),
    .DRDY (mmcm_ready_s),
    .DWE (mmcm_wr),
    .PSCLK (1'b0),
    .PSEN (1'b0),
    .PSINCDEC (1'b0),
    .PSDONE (),
    .LOCKED (mmcm_locked_s),
    .PWRDWN (1'b0),
    .RST (mmcm_rst));


FCVO = (1000 *  CLKFBOUT_MULT_F (49.000)) /( DIVCLK_DIVIDE (11) *  CLKIN1_PERIOD (5.000)) where its value is 890.90. However, the planahead reports the value to be 222.727273 = 890.90/4. I don't understand why it cause the problem.

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2 Replies
Xilinx Employee
Xilinx Employee
Registered: ‎07-23-2012

Re: Valid FCVO value

Hi Peter,

If you have a period constraint defined on the input clock to mmcm then that value will take precedence over the period value specified in HDL.

Please check if you have any period constraints defined in the .ucf and correct it accordingly.

Please mark the post as "Accept as solution" if the information provided answers your query/resolves your issue.

Give Kudos to a post which you think is helpful.
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Community Manager
Community Manager
Registered: ‎06-14-2012

Re: Valid FCVO value

When an MMCM is generated in Coregen or instantiated, some factors (Such as CLKFBOUT_MULT_F, CLKFBOUT_MULT_F) are fixed.
In DRC check for FVCO,
CLKIN1_PERIOD is from period constraint of UCF.
When you get this error message, the period constraint for the input of MMCM must be different from the frequency set in Coregen.
When you use the correct period constraint for the input of MMCM, the issue can be solved.  Can you check that?

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