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Visitor cfrick
Visitor
168 Views
Registered: ‎12-11-2018

Virtex Ultrascale Plus GTE4 BUF_GT / GT Sub-optimal Placement

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Hello,

In working on a project I'm coming across and issue regarding the placement of IBUFDS_GTE4 and GT component pair placements. Overall this is in regards to the placement of reference clocks into the Ultrascale Transcievers IP v1.7.

It is very similar to the following question thread here: https://forums.xilinx.com/t5/Implementation/Sub-optimal-placement-for-an-IBUFDS-GT-GT-component-pair/td-p/724358

However the message is different:

[Place 30-739] Sub-optimal placement for an IBUFDS_GT / GT component pair.Processing will continue as all instances of this rule have been LOCed.

refclk_io_gen[1].mgt_refclk_ibuf[0] (IBUFDS_GTE4.O) is locked to GTYE4_COMMON_X0Y7 (in SLR 1)
jesd204_top/vup_gty_top/vup_gty_ip_top/vup_gty/inst/gen_gtwizard_gtye4_top.vup_gty_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[3].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST (GTYE4_CHANNEL.GTREFCLK0) is locked to GTYE4_CHANNEL_X0Y12 (in SLR 0)
jesd204_top/vup_gty_top/vup_gty_ip_top/vup_gty/inst/gen_gtwizard_gtye4_top.vup_gty_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[3].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST (GTYE4_CHANNEL.GTREFCLK0) is locked to GTYE4_CHANNEL_X0Y13 (in SLR 0)
jesd204_top/vup_gty_top/vup_gty_ip_top/vup_gty/inst/gen_gtwizard_gtye4_top.vup_gty_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[3].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST (GTYE4_CHANNEL.GTREFCLK0) is locked to GTYE4_CHANNEL_X0Y14 (in SLR 0)
and jesd204_top/vup_gty_top/vup_gty_ip_top/vup_gty/inst/gen_gtwizard_gtye4_top.vup_gty_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[3].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST (GTYE4_CHANNEL.GTREFCLK0) is locked to GTYE4_CHANNEL_X0Y15 (in SLR 0)

 

Looks like the clock is crossing between different SLR sections of the chip. What is the best way to go about fixing this situation? In the thread linked above, one of the solutions mentions specifying the correct location of the GT channels and GT reference clocks, but how is this specified for the IP? Presently the channels are mapped as the following for the XCVU9P chip:

DP0 to 3: Quad Bank 121 (X0Y2 SLR0)

DP4 to 7: Quad Bank 126 (X0Y7 SLR1)

DP8 to 11: Quad Bank 122 (X0Y3 SLR0)

DP12 to 15: Quad Bank 125 (X0Y6 SLR1)

Each pair of reference clocks MGTREFCLK0/1 is supplied with clocks into the Banks 121, 126, 122 and 125.

Any insight here is appreciated. Thank you!

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Visitor cfrick
Visitor
129 Views
Registered: ‎12-11-2018

Re: Virtex Ultrascale Plus GTE4 BUF_GT / GT Sub-optimal Placement

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I solved my own issue. Turns out the way the reference clocks were being passed to the GTY IP had the wrong reference clocks associated with each of the GTYE4 Common Primitives. Once I determined the proper enumeration of the quads, I was able to identify which output from the IBUFDS_GTE4 was supposed to be fed to which of the Common Primitives.

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1 Reply
Visitor cfrick
Visitor
130 Views
Registered: ‎12-11-2018

Re: Virtex Ultrascale Plus GTE4 BUF_GT / GT Sub-optimal Placement

Jump to solution

I solved my own issue. Turns out the way the reference clocks were being passed to the GTY IP had the wrong reference clocks associated with each of the GTYE4 Common Primitives. Once I determined the proper enumeration of the quads, I was able to identify which output from the IBUFDS_GTE4 was supposed to be fed to which of the Common Primitives.

0 Kudos