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Observer tullio
Registered: ‎01-13-2009

Virtex5 with banks at different IOSTANDARD voltages

I want to share my experience, as I could not find anything similar on xilinx.com

I have a ISE13.4 design with a Virtex5 and a few hundreds pins at various standards including LVCMOS15, LVCMOS33, LVDS, and MGT lines.

I do the assignement writing directly the ucf file.

Initially I made the IOSTANDARD assignemnts like;

NET "rxRdy"       IOSTANDARD = LVCMOS15;

without making LOC assignemnts.

The idea was in order to make a quick ucf compatible with my IO requirements, and let the tool assign the optimal pins


In this case Mapper would fail with various error messages, normally not documented (some of them about LVDS RPM, other ones about MGT clock and data not matching, etc).


Then I decided to do the LOC assignemnt first, and the PAR completed ok.

At that point I also added the IOSTANDARD and again PAR completed ok.


Regarding my initial approach, it seems to me that on a certain step ISE assigns the pins, and a later steps find that those locations are not legal.



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2 Replies
Community Manager
Community Manager
Registered: ‎06-14-2012

Re: Virtex5 with banks at different IOSTANDARD voltages


yes. Its highly recommended that you loc your pins according to your usage in the design. The tools chose the defaults  and sometimes it might create a conflict. Ideally we catch these scenarios and try to improve our tools.


As a designer, I would definitely favour locing your pins in your design as per our requirement aligning with SelectIO guidelines.


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Registered: ‎02-25-2008

Re: Virtex5 with banks at different IOSTANDARD voltages

Always use LOC constraints on your pins.


You need to make a PCB. You can't have random pin assignments, right?

----------------------------Yes, I do this for a living.
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