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Observer myth785k
Observer
4,408 Views
Registered: ‎12-05-2010

Virtex6 Temac GMII clock placement issues.

Moving XPS generated Microblaze + DDR3 + Ethernet design (Hard Temac based) + AVB endpoint from ML605 to custom virtex6 board VLX240T1759 failing with Map error. The Gmii RX clock signal somehow could not be locked to AJ40 Pin. All other signals are mapped and routed normally. The Global buffering generation is done by XPS GUI. Same design (just different ucf file) working just fine in ML605. Have tried to get explanation in PlanAhead , but could not get anything unusual, just same error the signal cannot be placed on TIEOFF_X0Y96. The constraints are following :

 

 

Net fpga_0_Hard_Ethernet_MAC_GMII_TX_CLK_0_pin LOC=AJ42  |  IOSTANDARD = LVCMOS25 | PERIOD =  125 MHz HIGH 50 %;

Net fpga_0_Hard_Ethernet_MAC_GMII_RX_CLK_0_pin LOC=AJ40  |  IOSTANDARD = LVCMOS25 | PERIOD =  125 MHz HIGH 50 % | IOB = force;

 

 

INST "*Hard_Ethernet_MAC/Hard_Ethernet_MAC/V6HARD_SYS.I_TEMAC/SINGLE_GMII.IO_YES_01.bufr_rx_0" LOC = "BUFR_X2Y7";

INST "*Hard_Ethernet_MAC/Hard_Ethernet_MAC/V6HARD_SYS.I_TEMAC/SINGLE_GMII.IO_YES_01.bufio_rx_0" LOC = "BUFIODQS_X0Y8";

INST "*Hard_Ethernet_MAC/Hard_Ethernet_MAC/V6HARD_SYS.I_TEMAC/SINGLE_GMII.I_EMAC_TOP/v5_emac_wrapper/v6_emac" LOC = "TEMAC_X0Y2";

Please help to solve this problem I have spent already 2 days fixing it. 
The tool set version is 12.2.

 

 

 

ERROR:Place:1073 - Placer was unable to create RPM[BUFIO_RPMs] for the component
   microblaze/main_inst/Hard_Ethernet_MAC/Hard_Ethernet_MAC/V6HARD_SYS.I_TEMAC/S
   INGLE_GMII.IO_YES_01.bufio_rx_0 of type BUFIO for the following reason.
   The reason for this issue:
   All of the logic associated with this structure is locked and the relative
   placement of the logic violates the structure. The problem was found between
   the relative placement of BUFIO
   microblaze/main_inst/Hard_Ethernet_MAC/Hard_Ethernet_MAC/V6HARD_SYS.I_TEMAC/S
   INGLE_GMII.IO_YES_01.bufio_rx_0 at site BUFIODQS_X0Y8 and IOB
   fpga_0_Hard_Ethernet_MAC_GMII_RX_CLK_0_pin at site IOB_X0Y96.  The following
   components are part of this structure:
ERROR:Pack:1654 - The timing-driven placement phase encountered an error.

 

ERROR:Place:1073 - Placer was unable to create RPM[BUFIO_RPMs] for the component   microblaze/main_inst/Hard_Ethernet_MAC/Hard_Ethernet_MAC/V6HARD_SYS.I_TEMAC/S   INGLE_GMII.IO_YES_01.bufio_rx_0 of type BUFIO for the following reason.   The reason for this issue:   All of the logic associated with this structure is locked and the relative   placement of the logic violates the structure. The problem was found between   the relative placement of BUFIO   microblaze/main_inst/Hard_Ethernet_MAC/Hard_Ethernet_MAC/V6HARD_SYS.I_TEMAC/S   INGLE_GMII.IO_YES_01.bufio_rx_0 at site BUFIODQS_X0Y8 and IOB   fpga_0_Hard_Ethernet_MAC_GMII_RX_CLK_0_pin at site IOB_X0Y96.  The following   components are part of this structure:ERROR:Pack:1654 - The timing-driven placement phase encountered an error.

 

Thanks !!!!!!

Sergey Sardaryan
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3 Replies
Xilinx Employee
Xilinx Employee
4,377 Views
Registered: ‎07-01-2008

Re: Virtex6 Temac GMII clock placement issues.

The placer doesn't like the relative placement of the BUFIO and IOB. The BUFIO is LOC'd. The first thing to check is whether the IOB is also LOC'd. What device package is invovled?

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Observer myth785k
Observer
4,364 Views
Registered: ‎12-05-2010

Re: Virtex6 Temac GMII clock placement issues.

Hello,

 

The device package is ff1759. Somehow compiler could not lock BUFIO primitive to that pin which is clock capable. I have cnanged the GMII RX clocking behavior in TEMAC wrapper which originally used BUFIO and BUFR (ideal solution for source sync signalling) to single BUFG. At least compiler is able "place and route" the design, however timing performance is poor.

 

I could not understand why  this pin is locked for BUFIO placement.

 

 

Sergey Sardaryan
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Voyager
Voyager
3,587 Views
Registered: ‎04-02-2011

Re: Virtex6 Temac GMII clock placement issues.

Hello,

 

The device package is ff1759. Somehow compiler could not lock BUFIO primitive to that pin which is clock capable. I have cnanged the GMII RX clocking behavior in TEMAC wrapper which originally used BUFIO and BUFR (ideal solution for source sync signalling) to single BUFG. At least compiler is able "place and route" the design, however timing performance is poor.

 

I could not understand why  this pin is locked for BUFIO placement.

 

 

Sergey Sardarya

 

With this if you are able to place & route,if the timing performance is poor,try with the Timing Analyser to find the slack between source & destination to find the root cause.

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