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Adventurer
Adventurer
2,618 Views
Registered: ‎10-17-2016

Vivado 12-1411 "Cannot set LOC property of ports" for a IBUFDS_DIFF_OUT

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Hi,

 

I'm using Vivado 2018.1 and I'm having troubles implementing a IBUFDS_DIFF_OUT that used to work with earlier versions of Vivado.

 

I need this buffer for a differential input of which I need both the positive and the negative signal.

 

The error message:

[Vivado 12-1411] Cannot set LOC property of ports, Illegal to place instance xxx/IBUFDS/IBUFDS_0/DIFFINBUF_INST on site HPIOBDIFFOUTBUF_X0Y79. The location site type (HPIOBDIFFOUTBUF) and bel type (HPIOBDIFFOUTBUF_DIFFOUTBUF) do not match the cell type (DIFFINBUF). Instance xxx/IBUFDS/IBUFDS_0/DIFFINBUF_INST belongs to a shape with reference instance rx_1_n. Shape elements have relative placement respect to each other. The invalid location might results from a constraint on any of the instance in the shape. ["xxx/constraints_xxx.xdc":28]

The constraint:

set_property PACKAGE_PIN V6 [get_ports rx_1_p]

After synthesis, the schematic shows two instances of DIFFINBUF. One with the p-input connected to DIFF_IN_P, the other with p-input connected to DIFF_IN_N.

 

How can I get rid of this error message?

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Adventurer
Adventurer
2,778 Views
Registered: ‎10-17-2016

Re: Vivado 12-1411 "Cannot set LOC property of ports" for a IBUFDS_DIFF_OUT

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Hi Marc,

 

TL;DR: When the critical warning occurs in one project, it will sort of transfer to other projects open at the same time. But the warning does not get stored to disk. Therefore, restarting Vivado will remove the warning.

 

Full Text:

After closing Vivado, I don't get the critical warning when I open any checkpoint or the full project anymore. Apparently, the problem is not stored to the files but must be in vivados memory. This is supported by the following observation:

 

When the problem had occurred in one project, say projectA, it would also occur in another project, say projectB, that was open at the same time. The warnings only appeared when I opened the schematics of the elaborated, synthesized or implemented designs. But once the warning had appeared, it would stay or reappear even after re-synthesis of the project. As the warning transfers from one project to another, I suspect there to be a problem The only way I found to get rid of it was to reset all output products, including the generated block designs. Maybe it would have been sufficient to just close vivado and open it again.

 

The problem was not occurring in every run, and it is well possible that you wont be able to reproduce it. If I remember correctly, the problem only occurred when I had multiple projects open at the same time. One of these projects was for an Artix-7 device, the other for the Zynq US+ 9EG ES2 device. Maybe this has caused the problem. The warning usually first appeared in the Zynq US+ project.

 

Since I haven't been working with an Artix-7 project anymore I did not have any more occurrences of the problem.

For me, the problem is solved because I have found a workaround (restarting Vivado). As it appears to be difficult to consistently reproduce the problem, I would suggest that I mark the problem as solved.

 

Best regards,

Tobias

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17 Replies
Moderator
Moderator
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Registered: ‎11-04-2010

Re: Vivado 12-1411 "Cannot set LOC property of ports" for a IBUFDS_DIFF_OUT

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Hi, @welo_zhaw ,
What's the detailed package information of your device?
Example format: xcku035-fbva900-2-e
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Adventurer
Adventurer
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Registered: ‎10-17-2016

Re: Vivado 12-1411 "Cannot set LOC property of ports" for a IBUFDS_DIFF_OUT

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Hi @hongh

I don‘t know by heart and I‘m out of office. It‘s the zcu102 board, ES2.

Regards, Tobias
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Moderator
Moderator
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Registered: ‎11-04-2010

Re: Vivado 12-1411 "Cannot set LOC property of ports" for a IBUFDS_DIFF_OUT

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Hi, @welo_zhaw ,

I fail to reproduce the issue you met.

Is the port for IBUFDS_DIFF_OUT used as clock? 

Please confirm that U6 is not used by the other port.

 

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Adventurer
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Registered: ‎10-17-2016

Re: Vivado 12-1411 "Cannot set LOC property of ports" for a IBUFDS_DIFF_OUT

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Hi @hongh

I use the port for a differential input, I verified in package pins view that they are correctly grouped.

The port is used for differential data input.

I will try in a new project to reproduce the problem.

Regards, Tobias
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Xilinx Employee
Xilinx Employee
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Registered: ‎05-08-2012

Re: Vivado 12-1411 "Cannot set LOC property of ports" for a IBUFDS_DIFF_OUT

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Hi @welo_zhaw. Is there connectivity to both an input and output port? The name implies an input buffer, but the site implies an output buffer. A schematic of the full connectivity might help.

 

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Adventurer
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Registered: ‎10-17-2016

Re: Vivado 12-1411 "Cannot set LOC property of ports" for a IBUFDS_DIFF_OUT

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Hi @marcb

 

The buffer I want to use is a differential input buffer with differential output.

 

The outputs of the buffer go to IDELAYE3 primitives, this should therefore not be a source of the problem.

 

This is what the Elaborated Design looks like:

 

schematic.png

 

And after Implementation:

schematic_impl.png

 

 

OK, this is strange, because the problem is not occurring anymore. When it wasn't working, the IBUFDS_DIFF_OUT was implemented using two DIFFINBUFs, one with rx_2_p and rx_2_n connected to DIFF_IN_P and DIFF_IN_N, and the other with the connections inverted. Only the O port of each DIFFINBUF was routed to a IBUFCTRL. This way, four IBUFCTRL would have been required, probably this was causing the placement failure.

Now, the implementation seems to work again, but it is unclear to me what actually fixed the problem. I have removed the top modules from the lock desgin, reset the output products and then added the modules again to the board design.

 

 

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Adventurer
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Registered: ‎10-17-2016

Re: Vivado 12-1411 "Cannot set LOC property of ports" for a IBUFDS_DIFF_OUT

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Hi @marcb,

 

the problem just reappeared after another run of implementation. This is what the schematic looks like after Implementation.

schematic_impl.png

 

I have no idea what is causing this.

 

The critical warning is:

[Vivado 12-1411] Cannot set LOC property of ports, Illegal to place instance xxx/US_PLUS_IDELAY.IBUFDS/IBUFDS_0/DIFFINBUF_INST on site HPIOBDIFFOUTBUF_X0Y69. The location site type (HPIOBDIFFOUTBUF) and bel type (HPIOBDIFFOUTBUF_DIFFOUTBUF) do not match the cell type (DIFFINBUF). Instance xxx/US_PLUS_IDELAY.IBUFDS/IBUFDS_0/DIFFINBUF_INST belongs to a shape with reference instance rx_2_n. Shape elements have relative placement respect to each other. The invalid location might results from a constraint on any of the instance in the shape. ["/xxx/srcs/io_serdes/constraints_zsync_zcu102.xdc":36]

 

 

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Moderator
Moderator
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Re: Vivado 12-1411 "Cannot set LOC property of ports" for a IBUFDS_DIFF_OUT

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Hi, @welo_zhaw ,

Do you mean with same synthesized result with different implementation strategies, sometimes the issue occurs, sometimes doesn't occur?

 

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Adventurer
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Re: Vivado 12-1411 "Cannot set LOC property of ports" for a IBUFDS_DIFF_OUT

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Hi @hongh

 

I had to check this first. After re-adding my IP as a module in the block design, I successfully ran the synthesis and implementation with the Vivado Synthesis 2017 Defaults and the Vivado Implementation 2017 Defaults (Using the Vivado 2018.1 toolchain).

I then changed to Vivado Synthesis 2018 Defaults and Vivado Implementation 2018 Defaults and then re-ran Synthesis and Implementation using Vivado 2018.1. This resulted in the problem described above.

 

Best regards,

Tobias

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Adventurer
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Re: Vivado 12-1411 "Cannot set LOC property of ports" for a IBUFDS_DIFF_OUT

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Edit: the critical warnings only occur when opening the Implemented Design.
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Xilinx Employee
Xilinx Employee
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Re: Vivado 12-1411 "Cannot set LOC property of ports" for a IBUFDS_DIFF_OUT

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Hi @welo_zhaw. Are the two logs available for comparison? It appears that the IBUFDS_DIFF_OUT macro is being expanded differently. Hopefully, this will show why the results are different.

 

 

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Adventurer
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Re: Vivado 12-1411 "Cannot set LOC property of ports" for a IBUFDS_DIFF_OUT

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Hi @marcb

 

I don't think I have to log files of both runs anymore. If you send me instructions which log you need I will try to get a good and bad example.

 

Would a checkpoint contain the necessary info?

 

Regards,

Tobias

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Re: Vivado 12-1411 "Cannot set LOC property of ports" for a IBUFDS_DIFF_OUT

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Hi @welo_zhaw,
You can post the runme.log file in both XX.runs/synth_1 and XX.runs/impl_1.
In the run with warning, does the synthesized design look like same as the implemented one?
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Re: Vivado 12-1411 "Cannot set LOC property of ports" for a IBUFDS_DIFF_OUT

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Hi @hongh

 

I can confirm that when the error occurs, both the synthesized and the implemented designs look the same.

 

I will attach log files to this post from a good and a bad run.

 

And I have found a way to provoke the warning:

If I run synthesis/implementation of the design while another project is open in vivado, the warning will be issued. These two projects use the same source files, but they have their own project directory each. One project (zcu102 board) uses my IP as a module in a block design. The bd is stored in the project directory, not in the source directory. The second project (for an ac701 board) has a vhdl top level file instantiating my IP. The warning can occur in either of the two projects.

 

Regards,

Tobias

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Xilinx Employee
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Re: Vivado 12-1411 "Cannot set LOC property of ports" for a IBUFDS_DIFF_OUT

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Hi @welo_zhaw. Thanks for the logs. Unfortunately, this did not uncover any more information. Besides the below line of the macro expansion matching, so do the implementation checksums. This would normally indicate identical results.

 

IBUFDS_DIFF_OUT => IBUFDS_DIFF_OUT (DIFFINBUF, IBUFCTRL, IBUFCTRL): 1 instances

 

Is the failing version of the project available to send?

 

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Adventurer
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Registered: ‎10-17-2016

Re: Vivado 12-1411 "Cannot set LOC property of ports" for a IBUFDS_DIFF_OUT

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Hi @marcb

 

yes, I can send you the failing version of the project. Can I send it to you in private?

 

Regards, Tobias

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Adventurer
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Registered: ‎10-17-2016

Re: Vivado 12-1411 "Cannot set LOC property of ports" for a IBUFDS_DIFF_OUT

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Hi Marc,

 

TL;DR: When the critical warning occurs in one project, it will sort of transfer to other projects open at the same time. But the warning does not get stored to disk. Therefore, restarting Vivado will remove the warning.

 

Full Text:

After closing Vivado, I don't get the critical warning when I open any checkpoint or the full project anymore. Apparently, the problem is not stored to the files but must be in vivados memory. This is supported by the following observation:

 

When the problem had occurred in one project, say projectA, it would also occur in another project, say projectB, that was open at the same time. The warnings only appeared when I opened the schematics of the elaborated, synthesized or implemented designs. But once the warning had appeared, it would stay or reappear even after re-synthesis of the project. As the warning transfers from one project to another, I suspect there to be a problem The only way I found to get rid of it was to reset all output products, including the generated block designs. Maybe it would have been sufficient to just close vivado and open it again.

 

The problem was not occurring in every run, and it is well possible that you wont be able to reproduce it. If I remember correctly, the problem only occurred when I had multiple projects open at the same time. One of these projects was for an Artix-7 device, the other for the Zynq US+ 9EG ES2 device. Maybe this has caused the problem. The warning usually first appeared in the Zynq US+ project.

 

Since I haven't been working with an Artix-7 project anymore I did not have any more occurrences of the problem.

For me, the problem is solved because I have found a workaround (restarting Vivado). As it appears to be difficult to consistently reproduce the problem, I would suggest that I mark the problem as solved.

 

Best regards,

Tobias

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