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Visitor aamir5253
Visitor
760 Views
Registered: ‎01-14-2018

Vivado 16.2 Placement Error (30-512)

Hi,

 

I am working on a project which has been upgraded to vivado from ISE. We have a block diaram in which are using axi_ethernet_interface to communicate with the block diagram and it was working perfectly until we upgraded to Vivado 16.2.

 

After the upgrade for some reason it is not able to do the placement and gives me this error.

 

ERROR: [Place 30-512] Clock region assignment has failed. Clock buffer 'microblaze_i/axi_ethernet_0/U0/eth_mac/U0/tri_mode_ethernet_mac_i/gmii_interface/bufio_gmii_rx_clk' (BUFIO) is placed at site BUFIO_X0Y12 in CLOCKREGION_X0Y3. Its loads need to be placed in the area enclosed by clock regions CLOCKREGION_X0Y3 and CLOCKREGION_X0Y3. One of its loads 'microblaze_i/axi_ethernet_0/U0/eth_mac/U0/tri_mode_ethernet_mac_i/gmii_interface/rx_er_to_mac_reg' (FDRE) is placed in site ILOGIC_X1Y149 in CLOCKREGION_X1Y2 which is outside the permissible area.
Resolution: Please ensure that clock buffer loads are placed within its reachable clock regions.

 

In the previous design we were not having this IOBUF which it complains about and now in the new design it places this IOBUF for some reason. It might be due to the update of the microblaze or the ethernet core because the project was done some years ago and we need to upgrade it to the latest tools and firmware we have. 

 

I have attached 3 pictures:

 

1. Previous design 

 

2. FDRE which it been placed in a slice and i guess vivado is complaining about this FDRE.

 

3. Another picture for the FDRE to make things clear.

 

Kindly help me in this regard.

 

Thanks,

 

Aamir Hussain

 

Previous_design.JPG
FDRE_complain.JPG
rx_er_to_mac_reg.JPG
0 Kudos
1 Reply
Xilinx Employee
Xilinx Employee
699 Views
Registered: ‎05-08-2012

Re: Vivado 16.2 Placement Error (30-512)

Hi @aamir5253. I would check the IP customization to see if there are clocking options that would allow you to choose different clock buffers. The BUFIO is limited to driving logic in one clock region. Having this BUFIO drive multiple clock regions is causing the error. The alternative would be to make sure all loads are contained within the same clock region.

 

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