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tud_hartmann
Adventurer
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Registered: ‎02-24-2012

[Vivado 2014.4] Abnormal program termination (11) in power_opt_design

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Hello,

 

I'm trying to port a design from Kintex-7 to Kintex UltraScale (xcku040-ffva1156-2-e). Synthesis runs without any problems. However, power_opt_design outputs the following:

 

# power_opt_design
Command: power_opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xcku040'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xcku040'
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 4.1: Begin power optimizations | Checksum: d6a5d713
INFO: [Pwropt 34-50] Optimizing power for module test_ethernet ...
INFO: [Pwropt 34-207] Design is in partially-placed state. Running in partially-placed mode.
PSMgr Creation: Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1901.488 ; gain = 0.000 ; free physical = 2403 ; free virtual = 21392
Found 76 new always-off flops by back propagation
Pre-processing: Time (s): cpu = 00:00:00.66 ; elapsed = 00:00:00.63 . Memory (MB): peak = 1909.496 ; gain = 8.008 ; free physical = 2393 ; free virtual = 21382
INFO: [Pwropt 34-9] Applying IDT optimizations ...
IDT: Time (s): cpu = 00:00:00.79 ; elapsed = 00:00:00.82 . Memory (MB): peak = 1926.504 ; gain = 17.008 ; free physical = 2371 ; free virtual = 21360
INFO: [Pwropt 34-10] Applying ODC optimizations ...
INFO: [Pwropt 34-215] Skipped ODC enables for 214 nets in BRAM flops in bus-based analysis.
INFO: [Pwropt 34-214] Skipped ODC enables for 42 nets in BRAM adress flops in bus-based analysis.
ODC: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1946.504 ; gain = 20.000 ; free physical = 2350 ; free virtual = 21339
Power optimization passes: Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1946.504 ; gain = 45.016 ; free physical = 2349 ; free virtual = 21339

INFO: [Pwropt 34-77] Creating clock enable groups ...
INFO: [Pwropt 34-96] Including small groups for filtering based on enable probabilities.
 Done
Grouping enables: Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1946.504 ; gain = 0.000 ; free physical = 2349 ; free virtual = 21339


Starting PowerOpt Patch Enables Task
INFO: [Pwropt 34-26] Patching clock gating enable signals for design test_ethernet ...
INFO: [Pwropt 34-162] WRITE_MODE attribute of 5 BRAM(s) out of a total of 21 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated.
INFO: [Pwropt 34-201] Structural ODC has moved 7 WE to EN ports
INFO: [Pwropt 34-100] Patcher adaptive clustering : original ram clusters 25 accepted clusters 12
Abnormal program termination (11)

 

Stack trace:

#
# An unexpected error has occurred (11)
#
Stack:
/lib64/libc.so.6(+0x387a0) [0x7fa3fd9747a0]
/opt/cad/xilinx/Vivado/2014.4/lib/lnx64.o/librdi_pwropt.so(HACOOPatcher::enableLikelyToSavePower(HACOOEnableGroup*)+0x146) [0x7fa3d1999186]
/opt/cad/xilinx/Vivado/2014.4/lib/lnx64.o/librdi_pwropt.so(HACOOPatcher::adaptiveFilterClusters(HSTVector<HACOOEnableGroup*, std::allocator<HACOOEnableGroup*> >&, bool)+0xd23) [0x7fa3d19a5ae3]
/opt/cad/xilinx/Vivado/2014.4/lib/lnx64.o/librdi_pwropt.so(HACOOPatcher::ApplyClockEnables(HSTVector<HACOOEnableGroup*, std::allocator<HACOOEnableGroup*> >*, char const*)+0x2ac) [0x7fa3d19acb8c]
/opt/cad/xilinx/Vivado/2014.4/lib/lnx64.o/librdi_pwropt.so(HACOOPwrOptMgr::patchEnables(HFLFloorplan*, HANENetlist const*, HDLHInstance*, HSTVector<HACOOEnableGroup*, std::allocator<HACOOEnableGroup*> >&, bool)+0x913) [0x7fa3d19b0a93]
/opt/cad/xilinx/Vivado/2014.4/lib/lnx64.o/librdi_pwropt.so(HACOOPwrOptMgr::pwroptInstance(HFLFloorplan*, HANENetlist*, HDLHInstance*, bool, bool)+0xb69) [0x7fa3d198cce9]
/opt/cad/xilinx/Vivado/2014.4/lib/lnx64.o/librdi_pwropt.so(HACOOPwrOpt::pwroptMain(HFLFloorplan*, HANENetlist const*, HSTVector<char const*, std::allocator<char const*> >&, HSTMap<HDLHNet const*, double, std::less<HDLHNet const*>, std::allocator<double> >&, HSTMap<HDLHNet const*, HSTSet<HSTString, std::less<HSTString>, std::allocator<HSTString> >, std::less<HDLHNet const*>, std::allocator<HSTSet<HSTString, std::less<HSTString>, std::allocator<HSTString> > > >&, HACOOClkGatingOptions*, bool, HSTVector<HDLHCellview*, std::allocator<HDLHCellview*> >&, HACOOPwrOpt::effort_level, HDGUIStatus*, bool, bool)+0x628) [0x7fa3d198d628]
/opt/cad/xilinx/Vivado/2014.4/lib/lnx64.o/librdi_vivadotasks.so(+0x1b2450) [0x7fa3d26d1450]
/opt/cad/xilinx/Vivado/2014.4/lib/lnx64.o/librdi_vivadotasks.so(+0x1b2f63) [0x7fa3d26d1f63]
/opt/cad/xilinx/Vivado/2014.4/lib/lnx64.o/librdi_common.so(+0x556583) [0x7fa3fe95c583]
/opt/cad/xilinx/Vivado/2014.4/lib/lnx64.o/libtcl8.5.so(+0x331f5) [0x7fa3f986d1f5]
/opt/cad/xilinx/Vivado/2014.4/lib/lnx64.o/libtcl8.5.so(+0x34d6b) [0x7fa3f986ed6b]
/opt/cad/xilinx/Vivado/2014.4/lib/lnx64.o/libtcl8.5.so(Tcl_EvalEx+0x16) [0x7fa3f986f276]
/opt/cad/xilinx/Vivado/2014.4/lib/lnx64.o/libtcl8.5.so(Tcl_FSEvalFileEx+0x1d2) [0x7fa3f98d3d02]
/opt/cad/xilinx/Vivado/2014.4/lib/lnx64.o/librdi_commontasks.so(+0x2ca7f7) [0x7fa3f5bb77f7]
/opt/cad/xilinx/Vivado/2014.4/lib/lnx64.o/librdi_common.so(+0x556583) [0x7fa3fe95c583]
/opt/cad/xilinx/Vivado/2014.4/lib/lnx64.o/libtcl8.5.so(+0x331f5) [0x7fa3f986d1f5]
/opt/cad/xilinx/Vivado/2014.4/lib/lnx64.o/libtcl8.5.so(Tcl_EvalObjv+0x32) [0x7fa3f986d7e2]
/opt/cad/xilinx/Vivado/2014.4/lib/lnx64.o/libtcl8.5.so(TclEvalObjEx+0x322) [0x7fa3f986f5d2]
/opt/cad/xilinx/Vivado/2014.4/lib/lnx64.o/librdi_commontasks.so(+0x2ebb38) [0x7fa3f5bd8b38]
/opt/cad/xilinx/Vivado/2014.4/lib/lnx64.o/librdi_commontasks.so(+0x2ee8bd) [0x7fa3f5bdb8bd]
/opt/cad/xilinx/Vivado/2014.4/lib/lnx64.o/librdi_commontasks.so(+0x2e7163) [0x7fa3f5bd4163]
/opt/cad/xilinx/Vivado/2014.4/lib/lnx64.o/librdi_common.so(+0x556583) [0x7fa3fe95c583]
/opt/cad/xilinx/Vivado/2014.4/lib/lnx64.o/libtcl8.5.so(+0x331f5) [0x7fa3f986d1f5]
/opt/cad/xilinx/Vivado/2014.4/lib/lnx64.o/libtcl8.5.so(Tcl_EvalObjv+0x32) [0x7fa3f986d7e2]
/opt/cad/xilinx/Vivado/2014.4/lib/lnx64.o/libtcl8.5.so(TclEvalObjEx+0x322) [0x7fa3f986f5d2]
/opt/cad/xilinx/Vivado/2014.4/lib/lnx64.o/librdi_commonmain.so(+0x7550) [0x7fa3fe201550]
/opt/cad/xilinx/Vivado/2014.4/lib/lnx64.o/libtcl8.5.so(Tcl_Main+0x1d5) [0x7fa3f98da175]
/opt/cad/xilinx/Vivado/2014.4/lib/lnx64.o/librdi_common.so(+0x5854c9) [0x7fa3fe98b4c9]
/lib64/libpthread.so.0(+0x91da) [0x7fa3fd42d1da]
/lib64/libc.so.6(clone+0x6d) [0x7fa3fda2995d]

 Implementation runs successfully if I remove power_opt_design from my scripts.

 

Best,

 

Stephan

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vemulad
Xilinx Employee
Xilinx Employee
22,372 Views
Registered: ‎09-20-2012

Hi Stephan,

 

Wish you a happy New Year !!

 

As per the current status of CR this issue is planned for fix in Vivado 2015.1. But this may change based on priorities.

 

Once the CR is fixed I will post here.

 

Thanks,

Deepika.

Thanks,
Deepika.
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achutha
Xilinx Employee
Xilinx Employee
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Registered: ‎07-01-2010
This is seen in 2014.3 and fixed in 2014.4.Looks like regression.Can you share your design?

Regards,
Achutha
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siktap
Scholar
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Registered: ‎06-14-2012

Which  OS are you trying to run this on?

 

Regards

Sikta

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tud_hartmann
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Registered: ‎02-24-2012

Hi,

 

tried it on RHEL 5.5 and RHEL 5.11. Both crash at same position with almost identical stack trace.

I can share the post synthesis checkpoint. Would that be enough for you?

 

Best,

 

Stephan

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vemulad
Xilinx Employee
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Registered: ‎09-20-2012

Hi Stephan,

 

Open synthesized design and use the below command in TCL console to generate the DCP file

 

write_checkpoint post_synth.dcp

 

Share the DCP file generated along with implementation log file.

 

Thanks,

Deepika.

Thanks,
Deepika.
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tud_hartmann
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Registered: ‎02-24-2012

Hi Deepika,

 

please find attached the post synthesis checkpoint.

 

Step to reproduce:

> open_checkpoint post-synthesis.dcp
> opt_design -directive Explore
> power_opt_design

I left out the physical contraints cause those are not required for reproducing the problem. You may need the soft TEMAC license, but I guess you have it ;)

I sent a PM to you with the password to open the zip file.

 

Thanks and best regards,

 

Stephan

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tud_hartmann
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Registered: ‎02-24-2012

Reattached cause previous file seems to be corrupted.

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vemulad
Xilinx Employee
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Registered: ‎09-20-2012

Hi @tud_hartmann 

 

Thanks for sharing the checkpoint file.

 

I am able to recreate the issue in latest Vivado 2015.1 internal build. I have filed Change Request CR 841074 and addressed this issue to factory.

 

Thanks,

Deepika.

Thanks,
Deepika.
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tud_hartmann
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Registered: ‎02-24-2012

Hi,

 

thanks for the information. Is this fixed in Vivado 2015.1?

 

Best Regards and happy new year :),

 

Stephan

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vemulad
Xilinx Employee
Xilinx Employee
22,373 Views
Registered: ‎09-20-2012

Hi Stephan,

 

Wish you a happy New Year !!

 

As per the current status of CR this issue is planned for fix in Vivado 2015.1. But this may change based on priorities.

 

Once the CR is fixed I will post here.

 

Thanks,

Deepika.

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
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tud_hartmann
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Registered: ‎02-24-2012

Just rechecked and it seems to be fixed in Vivado 2015.1.

 

Thanks,

 

Stephan

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