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arvindnr
Voyager
Voyager
7,274 Views
Registered: ‎02-10-2012

Vivado 2015.5 uses more block ram resources in implementation compared to vivado 2014.4

Hey

 

I had a fully routed finalized design in vivado 2014.4 which used 98 percent of the block ram of the Zynq 7Z030fbg676-2 chip . I recently upgraded to vivado 2015.4 and just tried to run implementation after the import process and the implementation fails stating that the block ram usage is 100 percent and it could not place certian portions of the block ram!  This is a bit suprising. All I did was just import the design , upgrade IP's (MMCM, FIFO's , etc ) to the latest version. I even used the same implementation and synthesis strategy as in 2014.4. The synthesis strategy is Flow_PerfOptimized_High and Implementation strategy is Performance_Explorer

 

I know 98 percent is on the very edge but it still did fit with the 2014.4 tools. Is there something I am missing ? 

 

Cheers

Arvind

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2 Replies
arpansur
Moderator
Moderator
7,270 Views
Registered: ‎07-01-2015

Hi @arvindnr,

 

Please share utilization report of the design for both the versions.

 

Thanks,
Arpan

Thanks,
Arpan
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siktap
Scholar
Scholar
7,166 Views
Registered: ‎06-14-2012

Thats right. Its on a edge. One more thing that could help is to lock the placement from the earlier run.

Open 2014.4 placed and routed dcp.

 

set_property IS_LOC_FIXED 1 [get_cells -filter {PRIMITIVE_LEVEL==LEAF} -hier *]

 set_property IS_BEL_FIXED 1 [get_cells -filter {PRIMITIVE_LEVEL==LEAF} -hier *]
write_xdc exclude_timing placement.xdc
 
Use this xdc in your project in 2015.4. If you are ok to share the testcase, we can file a regression CR on tools. 
 
Regards
Sikta
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