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Adventurer
Adventurer
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Registered: ‎07-24-2018

Vivado 2016.1 Implementation Error -

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I've been trying to translate the image processing design targeting the Zybo board here (http://web-pcm.cnfm.fr/wp-content/uploads/2017/04/Workbook-Digilent_ZYBO_Video_Workshop.pdf) for the Arty-Z7-20.  My design validates and Synthesizes fine.  However, I get an error during Implementation that I can't seem to resolve.  

 

 

Block design is:

pynq_hdmi_in_out_architecture.jpg

 

Constraints file is here:

#clock
set_property -dict { PACKAGE_PIN H16    IOSTANDARD LVCMOS33 } [get_ports { sys_clock }]; IO_L13P_T2_MRCC_35 [get_ports { sys_clock }]

#hdmi in
set_property -dict { PACKAGE_PIN P19   IOSTANDARD TMDS_33  } [get_ports { hdmi_in_clk_n }]; 
set_property -dict { PACKAGE_PIN N18   IOSTANDARD TMDS_33  } [get_ports { hdmi_in_clk_p }]; 
set_property -dict { PACKAGE_PIN W20   IOSTANDARD TMDS_33  } [get_ports { hdmi_in_data_n[0] }]; 
set_property -dict { PACKAGE_PIN V20   IOSTANDARD TMDS_33  } [get_ports { hdmi_in_data_p[0] }]; 
set_property -dict { PACKAGE_PIN U20   IOSTANDARD TMDS_33  } [get_ports { hdmi_in_data_n[1] }]; 
set_property -dict { PACKAGE_PIN T20   IOSTANDARD TMDS_33  } [get_ports { hdmi_in_data_p[1] }]; 
set_property -dict { PACKAGE_PIN P20   IOSTANDARD TMDS_33  } [get_ports { hdmi_in_data_n[2] }]; 
set_property -dict { PACKAGE_PIN N20   IOSTANDARD TMDS_33  } [get_ports { hdmi_in_data_p[2] }]; 
set_property -dict { PACKAGE_PIN U14   IOSTANDARD LVCMOS33 } [get_ports { hdmi_in_ddc_scl_io }]; 
set_property -dict { PACKAGE_PIN U15   IOSTANDARD LVCMOS33 } [get_ports { hdmi_in_ddc_sda_io }]; 


#hdmi out
set_property -dict { PACKAGE_PIN L17   IOSTANDARD TMDS_33  } [get_ports  hdmi_out_clk_n]; 
set_property -dict { PACKAGE_PIN L16   IOSTANDARD TMDS_33  } [get_ports  hdmi_out_clk_p ]; 
set_property -dict { PACKAGE_PIN K18   IOSTANDARD TMDS_33  } [get_ports { hdmi_out_data_n[0] }]; 
set_property -dict { PACKAGE_PIN K17   IOSTANDARD TMDS_33  } [get_ports { hdmi_out_data_p[0] }]; 
set_property -dict { PACKAGE_PIN J19   IOSTANDARD TMDS_33  } [get_ports { hdmi_out_data_n[1] }]; 
set_property -dict { PACKAGE_PIN K19   IOSTANDARD TMDS_33  } [get_ports { hdmi_out_data_p[1] }]; 
set_property -dict { PACKAGE_PIN H18   IOSTANDARD TMDS_33  } [get_ports { hdmi_out_data_n[2] }]; 
set_property -dict { PACKAGE_PIN J18   IOSTANDARD TMDS_33  } [get_ports { hdmi_out_data_p[2] }]; 
set_property -dict { PACKAGE_PIN R19   IOSTANDARD LVCMOS33 } [get_ports { hdmi_hpd }];

The error message is:

error_message.jpg

Per the tutorial, I modified the clocking wizard to output a 200Mhz signal.  Lastly, per the tutorial, I modified the dvi2rgb core as such:

 

dvi2rgb.jpg

 

It appears to me that the clocking issue with the dvi2rgb core is what is causing all the other issues but I'm sure of how to modify my design to make this work.  Any help would be greatly appreciated!

error_message.jpg
pynq_hdmi_in_out_architecture.jpg
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Moderator
Moderator
1,267 Views
Registered: ‎01-16-2013

Re: Vivado 2016.1 Implementation Error -

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@dcc3

 

Can you try locking the MMCM to the same clock region of oserdes and see if it helps:

You can try locking MMCM to the same clock region of ISERDES. 

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_1/ug912-vivado-properties.pdf#page=245

 

The command should be something similar to: 

set_property LOC MMCME2_ADV_XxYy [get_cells design_1_i/rgb2dvi_0/U0/ClockGenInternal.ClockGenX/GenMMCM.DVI_ClkGenerator]

 

Note: In the above command, you need to correctly mention the MMCM site location which is present in the required clock region. 

 

--Syed

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Xilinx Employee
Xilinx Employee
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Registered: ‎05-08-2012

Re: Vivado 2016.1 Implementation Error -

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Hi @dcc3. In your Clocking Wizard IP, does do the output clocks drive a global buffer? This would allow for more than one clock region to be driven.

 


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Adventurer
Adventurer
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Registered: ‎07-24-2018

Re: Vivado 2016.1 Implementation Error -

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@marcb

 

Currently the clock wizard is using the default where it drives a BUFG:

 

clock_wizard_settings.jpg

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Moderator
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Registered: ‎01-16-2013

Re: Vivado 2016.1 Implementation Error -

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@dcc3

 

Can you share vivado archive project to debug the issue? 

 

--Syed

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
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Did you check our new quick reference timing closure guide (UG1292)?
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Adventurer
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Registered: ‎07-24-2018

Re: Vivado 2016.1 Implementation Error -

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@syedz

 

Thanks for the help!  I've been reviewing the documentation on clock regions, buffers, etc. and I've yet to find a solution.

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Registered: ‎01-16-2013

Re: Vivado 2016.1 Implementation Error -

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@dcc3,

 

The shared design successfully passed PnR on my machine in 2016.1. Also the MMCM and its loads are present in same clock region. 

Capture.JPG

 

You can try locking MMCM to the same clock region of ISERDES. 

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_1/ug912-vivado-properties.pdf#page=245

 

--Syed

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------
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Adventurer
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1,279 Views
Registered: ‎07-24-2018

Re: Vivado 2016.1 Implementation Error -

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@syedz

 

Thanks for the recommendations but I have yet to resolve the issue.  After synthesizing I get the same pnr that you do:

 

pnr.jpg

 

However, during implementation I still get the same clock region error.  Since the archived project worked on your machine I asked two other students to attempt it and they got the same error as me.  They are both using webpack licenses (like me) if that could be a problem (maybe Vivado is restricted in optimization with the free version?).

 

I've tried the following three constraints attempting to force the rgb2div core to the same clock region and none have resolved it:

set_property CLOCK_DEDICATED_ROUTE=FALSE [get_nets design_1_i/rgb2dvi_0/U0/ClockGenInternal.ClockGenX/PixelClk]

 

set_property CLOCK_DEDICATED_ROUTE=BACKBONE [get_nets design_1_i/rgb2dvi_0/U0/ClockGenInternal.ClockGenX/PixelClk]

 

set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_pins -hier -filter {NAME =~ */design_1_i/rgb2dvi_0/U0/ClockGenInternal.ClockGenX/PixelClk}]

 

Additionally, I tried to use LOC as your suggested.  My schematic/cell list is below:

 

schematic.jpg

 

I believe I'm not using the LOC set property correctly because when I reload the the constraints I get a 'set_property expects at least one object' error.  The set property command I've tried with LOC is:

 

set_property LOC SLICE_X1Y1 [get_cells design_1_rgb2dvi_0_0]

 

 

 

 

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Moderator
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Registered: ‎01-16-2013

Re: Vivado 2016.1 Implementation Error -

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@dcc3

 

Can you try locking the MMCM to the same clock region of oserdes and see if it helps:

You can try locking MMCM to the same clock region of ISERDES. 

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_1/ug912-vivado-properties.pdf#page=245

 

The command should be something similar to: 

set_property LOC MMCME2_ADV_XxYy [get_cells design_1_i/rgb2dvi_0/U0/ClockGenInternal.ClockGenX/GenMMCM.DVI_ClkGenerator]

 

Note: In the above command, you need to correctly mention the MMCM site location which is present in the required clock region. 

 

--Syed

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------

View solution in original post

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Adventurer
Adventurer
1,259 Views
Registered: ‎07-24-2018

Re: Vivado 2016.1 Implementation Error -

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@syedz

 

By adding the following two constraints I was able to overcome the MMCM errors and successfully build a bitstream:

 

set_property LOC MMCME2_ADV_X1Y2 [get_cells design_1_i/rgb2dvi_0/U0/ClockGenInternal.ClockGenX/GenMMCM.DVI_ClkGenerator]
set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0]

 

Thanks for all the help.

 

Regrettably, the system still doesn't work as designed in that my hdmi monitor still doesn't recognize a signal.  Seems like that should be the topic of another post since you've solved this one.