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Adventurer
Adventurer
9,585 Views
Registered: ‎03-28-2014

Vivado 2016.1 inout termination/new DRC Error

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I have a Zynq based design that brings out the SPI through EMIO and the IO1 and SS bidirectional signals are unused. In previous versions of Vivado I was able to connect these ports to dummy signals and build without any trouble; however, I just updated to Vivado 2016.1 and am now getting the following DRC errors:

 

[DRC 23-20] Rule violation (NDRV-1) Driverless Nets - Net arm/spi_0_io1_i, arm/spi_0_ss_i are undriven.
[DRC 23-20] Rule violation (RTSTAT-6) Partial conflict - 3 net(s) have a partial conflict. The problem bus(es) and/or net(s) are arm/spi_0_io1_i, arm/spi_0_ss_i, GLOBAL_LOGIC0.

What is the proper method for terminating the unused bidirectional dignals from the Block Design in Vivado 2016.1?

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Xilinx Employee
Xilinx Employee
17,899 Views
Registered: ‎06-14-2012

Re: Vivado 2016.1 inout termination/new DRC Error

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There was a change in the behavior while dealing with driveless signals. Can you put a dont_touch on these unused dummy signals? There is a bug filed (CR 935451)

 

That will help you workaorund this for now. Hope this helps.

 

Regards

Sikta

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Xilinx Employee
Xilinx Employee
17,900 Views
Registered: ‎06-14-2012

Re: Vivado 2016.1 inout termination/new DRC Error

Jump to solution

There was a change in the behavior while dealing with driveless signals. Can you put a dont_touch on these unused dummy signals? There is a bug filed (CR 935451)

 

That will help you workaorund this for now. Hope this helps.

 

Regards

Sikta

View solution in original post

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Adventurer
Adventurer
9,256 Views
Registered: ‎03-28-2014

Re: Vivado 2016.1 inout termination/new DRC Error

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Thanks for the workaround Sikta. I haven't tested it yet since I've already reverted to an older version of Vivado, but I'll consider the problem solved.

 

-Dan

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