UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Observer elphel
Observer
5,624 Views
Registered: ‎08-09-2013

Vivado 2016.2 fails timing where 2015.3 does not

I tried to implement the same design (https://github.com/Elphel/x393) with Vivado 2016.2 as I did with 2015.3, and 2016 uses more resources and fails timing. I tried it with clean start (new project, just the same set of the Verilog sources and constraint files) and with two different options - our project can be configured either for parallel image sensors or for HISPI ones. All the synthesis and implementation tools parameters remained the same.

Is it a problem of the newer software, or the old one was too optimistic in timing and the new one is more realistic? Or maybe some defaults for the tools changed? Something else I can try to get the same results from the newer software as I did from the earlier version?

 

Design option2015.32016.2
Parallel imagers79.68% slices, timing met79.72%slices, 1 clock timing failed
HISPI imagers80.94% slices, timing met84.7% slices, 2 clocks timing failed
0 Kudos
2 Replies
Xilinx Employee
Xilinx Employee
5,154 Views
Registered: ‎09-20-2012

Re: Vivado 2016.2 fails timing where 2015.3 does not

Hi @elphel

 

How many endpoints are failing to meet timing in 2016.2?

 

Please check Critical warning messages and ensure that all constraints are accepted by the tool.

 

You can try using different Implementation strategies to meet timing on 2016.2 design.

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)
0 Kudos
Observer elphel
Observer
5,136 Views
Registered: ‎08-09-2013

Re: Vivado 2016.2 fails timing where 2015.3 does not

Hello Deepika,

 

I attached both timing summaries for 2015.3 and 2016.2. The difference is not big (also 2016.2 used more resources as I mentioned in the original post), here are the failing constraints:

 

Failing timing in 2016.2
ClockWNS(ns)TNS(ns)TNS Failing EndpointsTNS Total EndpointsWHS(ns)THS(ns)THS Failing EndpointsTHS Total EndpointsWPWS(ns)TPWS(ns)TPWS Failing EndpointsTPWS Total Endpoints
xclk-0.145-1.98535340590.0550.0000340590.8750.000012975
pclk-0.209-2.8864295360.0520.000095361.5060.00004675
Same constraints in 2015.3
ClockWNS(ns)TNS(ns)TNS Failing EndpointsTNS Total EndpointsWHS(ns)THS(ns)THS Failing EndpointsTHS Total EndpointsWPWS(ns)TPWS(ns)TPWS Failing EndpointsTPWS Total Endpoints
xclk0.0470.0000328330.0540.0000328330.8750.000013010
pclk0.2610.000093530.0530.000093531.3380.00004603

 

No critical warnings (software I use treats them as errors), same settings for both versions. I tried some minor variations (even 2015.3 is not always meeting timing), but was not able to get the same results as with older Vivado software.

 

It is not easy to do some coherent experimenting when I do not know what is the difference between the versions, my only assumptions were that while optimizing software for the new silicon (ultrascale) some internal settings/algorithms for the older Zynq became sub-optimal. I'll be happy to try some specific tweaking or just wait and test later version when it will become available.

 

Andrey

 

0 Kudos