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Visitor kaza
Visitor
872 Views
Registered: ‎12-16-2018

Vivado 2016.3 how to know if routing utilization close to full?

Hello!

 

I have a design which is synthesized/implemented by Vivado 2016.3.

The resource utilization after the implementation shows values quite far from full:

LUT: 42%

FF: 23%

BRAM: 21%

IO: 6%

GT: 55%

BUFG: 11%

PCIe: 33%

 

However the design shows signs of being close to routing resources utilization:

Openinig implemented design and looking at the device with utilized cells I see that they're

covering about 80% of the area of the device (when zooming in I see that there are gaps

of unused cells among the utilized cells in any region) and most importantly:

I can barely manage to fit within the timing constraints. A very small increase in logic

(like adding an ILA or slightly increasing the number of watched signals in existing ILA)

pushes the design over the timing constraints limits. The failing timing paths are random,

not specific to any module and when I mark them I see that they're caused by source-destination

FFs being quite far away and the wiring delay is very large. If I remove the added ILA or go back

to smaller one I can most of the time get back within the timing limits, sometimes not so I cancell

some more ILAs, geta a passing timing design, then I can most of the time return the last ILA

and get back to design passing timing and with some ILAs (not as many as I need to debug

comfortably).

 

Is this a behavior of a design which is close to routing utilization limit? How can I know how close

am I to this limit (it isn't reported among other resources utilization)?

 

The synthesys strategy was: "Flow PerfOptimized high",

The implementation strategy was: "Performance WLBlockPlacementFanoutOpt".

 

At the initial stages of the project I experimented with other strategies but they gave

worse results that these ones.

 

TIA,

kaza.

 

 

 

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8 Replies
Moderator
Moderator
868 Views
Registered: ‎01-16-2013

Re: Vivado 2016.3 how to know if routing utilization close to full?

@kaza

Are you seeing any messages related to congestion during route_design? Can you attach the vivado.log or runme.log present in <project>/<project>.runs/impl_1/runme.log

Check this AR on debugging congestion:

https://www.xilinx.com/support/answers/66314.html

 

--Syed

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Scholar watari
Scholar
865 Views
Registered: ‎06-16-2013

Re: Vivado 2016.3 how to know if routing utilization close to full?

Hi @kaza

 

It seems congestion issue.

Would you make sure fanout and bus width in your design ?

 

I guess your design has a specific architecture to dificulty do P&R and it might have to modify it.

 

Best regards,

Visitor kaza
Visitor
826 Views
Registered: ‎12-16-2018

Re: Vivado 2016.3 how to know if routing utilization close to full?

Hi syedz, thanks for the reply.

 

Yes, I'm seeing a congestion report in runme.log file:

 

Phase 4.1 Global Iteration 0
INFO: [Route 35-443] CLB routing congestion detected. Several CLBs have high routing utilization, which can impact timing closure. Top ten most congested CLBs are: CLE_M_X41Y179 CLEL_R_X41Y179 CLE_M_X44Y221 CLEL_R_X44Y221 CLE_M_X47Y180 CLEL_R_X47Y180 CLEL_L_X55Y241 CLEL_R_X55Y241 CLE_M_X41Y196 CLEL_R_X41Y196
 Number of Nodes with overlaps = 19769
 Number of Nodes with overlaps = 688
 Number of Nodes with overlaps = 29
 Number of Nodes with overlaps = 0

 

I've also run "report_high_fanout_nets" and the top 2 signals were clocks

17882 | BUFG_GT

12853 | BUFGCTRL

 

and a reset signal

6321 | FDCE

and the forth was also a clock signal

4449 | BUFG_GT

I guess, since these are clocks/resets the Vivado creates buffers tree which I can't

improve, right?

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Moderator
Moderator
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Registered: ‎01-16-2013

Re: Vivado 2016.3 how to know if routing utilization close to full?

@kaza

 

Check if the reset signal "6321 | FDCE" is causing the routing congestion. You can use report_design_analysis command to debug congestion. 

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_3/ug906-vivado-design-analysis.pdf#page=187

 

 

If you can migrate to the latest vivado 2018.3 then it has a new feature called "report_qor_suggestion":

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_3/ug906-vivado-design-analysis.pdf#page=155

 

--Syed

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Visitor kaza
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Registered: ‎12-16-2018

Re: Vivado 2016.3 how to know if routing utilization close to full?

I've run "report_design_analysys -congestion" and got this:

 

report_design_analysis -congestion
INFO: [Place 30-885] Complexity reporting was skipped for small modules in this design. Small modules have negligible contributions to the overall design complexity.
Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
--------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.3 (lin64) Build 1682563 Mon Oct 10 19:07:26 MDT 2016
| Date         : Mon Dec 17 13:16:41 2018
| Host         : asic-11 running 64-bit Red Hat Enterprise Linux Server release 7.5 (Maipo)
| Command      : report_design_analysis -congestion
| Design       : uo
| Device       : xcku040
--------------------------------------------------------------------------------------------

Report Design Analysis

Table of Contents
-----------------
1. Placed Maximum Level Congestion Reporting
2. Average Initial Router Maximum Congestion Reporting
3. Router Maximum Level Congestion Reporting
4. SLR Net Crossing Reporting
5. Placed Tile Based Congestion Metric (Vertical)
6. Placed Tile Based Congestion Metric (Horizontal)

1. Placed Maximum Level Congestion Reporting
--------------------------------------------

+-----------+------+------------+----------------------------------+------+-------------------------------+-----------+------------+-----------+--------------+--------------+-----------+
| Direction | Size | Congestion |         Congestion Window        | Rent |           Cell Names          | Lut Usage | Flop Usage | Mux Usage | Ramb18 Usage | Ramb36 Usage | Dsp Usage |
+-----------+------+------------+----------------------------------+------+-------------------------------+-----------+------------+-----------+--------------+--------------+-----------+
| North     | 2x2  | 102%       | (CLEL_R_X64Y256,CLE_M_R_X65Y257) | NA   | OCORES.OCORE[0].i_ocore(100%) | 87%       | 9%         | 7%        | NA           | NA           | NA        |
| East      | 1x1  | 72%        | (CLE_M_X53Y110,CLE_M_X53Y110)    | NA   | i_nt_top(100%)                | 50%       | 93%        | 0%        | NA           | NA           | NA        |
| South     | 1x1  | 75%        | (CLEL_R_X48Y103,CLEL_R_X48Y103)  | NA   | i_nt_top(100%)                | 75%       | 18%        | 0%        | NA           | NA           | NA        |
| West      | 1x1  | 59%        | (CLEL_R_X48Y140,CLEL_R_X48Y140)  | NA   | i_nt_top(100%)                | 50%       | 87%        | 0%        | NA           | NA           | NA        |
+-----------+------+------------+----------------------------------+------+-------------------------------+-----------+------------+-----------+--------------+--------------+-----------+
* NA - Not applicable or Rent cannot be calculated due to no relationship found between partition size and cuts.


2. Average Initial Router Maximum Congestion Reporting
------------------------------------------------------

+-----------+------+------------+---------------------------------+------+-------------------------------+-----------+------------+-----------+--------------+--------------+-----------+
| Direction | Size | Congestion |        Congestion Window        | Rent |           Cell Names          | Lut Usage | Flop Usage | Mux Usage | Ramb18 Usage | Ramb36 Usage | Dsp Usage |
+-----------+------+------------+---------------------------------+------+-------------------------------+-----------+------------+-----------+--------------+--------------+-----------+
| East      | 1x1  | 76%        | (CLEL_L_X64Y270,CLEL_L_X64Y270) | NA   | OCORES.OCORE[0].i_ocore(100%) | 75%       | 25%        | 14%       | NA           | NA           | NA        |
| East      | 1x1  | 76%        | (CLEL_L_X64Y259,CLEL_L_X64Y259) | NA   | uo(100%)                  | 62%       | 18%        | 0%        | NA           | NA           | NA        |
| East      | 1x1  | 76%        | (CLEL_L_X64Y257,CLEL_L_X64Y257) | NA   | OCORES.OCORE[0].i_ocore(100%) | 75%       | 37%        | 0%        | NA           | NA           | NA        |
+-----------+------+------------+---------------------------------+------+-------------------------------+-----------+------------+-----------+--------------+--------------+-----------+
* Congested regions with less than 95% congestion are not reported.
** NA - Not applicable or Rent cannot be calculated due to no relationship found between partition size and cuts.


3. Router Maximum Level Congestion Reporting
--------------------------------------------

+-----------+------+------------+-------------------+------+------------+-----------+------------+-----------+--------------+--------------+-----------+
| Direction | Size | Congestion | Congestion Window | Rent | Cell Names | Lut Usage | Flop Usage | Mux Usage | Ramb18 Usage | Ramb36 Usage | Dsp Usage |
+-----------+------+------------+-------------------+------+------------+-----------+------------+-----------+--------------+--------------+-----------+
* No router congested regions found.


4. SLR Net Crossing Reporting
-----------------------------

+------------+-----------------------------+
| Cell Names | Number of Nets crossing SLR |
+------------+-----------------------------+
* The current part is not an SSI device


5. Placed Tile Based Congestion Metric (Vertical)
-------------------------------------------------

+--------------+-----------------+--------------+----------------------+------------+---------------------+
|   Tile Name  | RPM Grid Column | RPM Grid Row | Congestion in Window | Cell Names | Placer Max Overlap? |
+--------------+-----------------+--------------+----------------------+------------+---------------------+
| CLEL_R_X56Y3 | 321             | 306          | 78%                  |            | N                   |
| CLEL_R_X56Y1 | 321             | 308          | 78%                  |            | N                   |
| CLEL_L_X57Y4 | 323             | 305          | 78%                  |            | N                   |
| CLEL_R_X56Y5 | 321             | 304          | 78%                  |            | N                   |
| CLEL_R_X56Y2 | 321             | 307          | 78%                  |            | N                   |
| CLEL_R_X56Y0 | 321             | 309          | 78%                  |            | N                   |
| CLEL_L_X57Y2 | 323             | 307          | 78%                  |            | N                   |
| CLEL_L_X57Y3 | 323             | 306          | 78%                  |            | N                   |
| CLEL_L_X57Y5 | 323             | 304          | 78%                  |            | N                   |
| CLEL_R_X56Y4 | 321             | 305          | 78%                  |            | N                   |
+--------------+-----------------+--------------+----------------------+------------+---------------------+


6. Placed Tile Based Congestion Metric (Horizontal)
---------------------------------------------------

+--------------+-----------------+--------------+----------------------+------------+---------------------+
|   Tile Name  | RPM Grid Column | RPM Grid Row | Congestion in Window | Cell Names | Placer Max Overlap? |
+--------------+-----------------+--------------+----------------------+------------+---------------------+
| CLEL_R_X56Y3 | 321             | 306          | 41%                  |            | N                   |
| CLEL_R_X56Y5 | 321             | 304          | 41%                  |            | N                   |
| CLEL_L_X57Y5 | 323             | 304          | 41%                  |            | N                   |
| CLEL_R_X56Y4 | 321             | 305          | 41%                  |            | N                   |
| CLEL_R_X56Y1 | 321             | 308          | 41%                  |            | N                   |
| CLEL_R_X56Y2 | 321             | 307          | 41%                  |            | N                   |
| CLEL_L_X57Y2 | 323             | 307          | 41%                  |            | N                   |
| CLEL_L_X57Y3 | 323             | 306          | 41%                  |            | N                   |
| CLEL_L_X57Y4 | 323             | 305          | 41%                  |            | N                   |
| CLEL_R_X56Y0 | 321             | 309          | 41%                  |            | N                   |
+--------------+-----------------+--------------+----------------------+------------+---------------------+


report_design_analysis: Time (s): cpu = 00:00:09 ; elapsed = 00:00:08 . Memory (MB): peak = 10427.883 ; gain = 0.000 ; free physical = 176475 ; free virtual = 253462

 

How can I use the output?

I don't see anything specifically pointing to the reset signal which has third largest fanout.

 

TIA,

kaza.

 

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Moderator
Moderator
793 Views
Registered: ‎01-16-2013

Re: Vivado 2016.3 how to know if routing utilization close to full?

@kaza

 

The design doesn't seem to be highly congested. Are all the nets getting routed successfully? If you can share the post opt dcp then we can have look.  

 

--Syed

 

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Visitor kaza
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Registered: ‎12-16-2018

Re: Vivado 2016.3 how to know if routing utilization close to full?

How should I get it? The various *.dcp files seems to be binaries...

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Moderator
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Registered: ‎01-16-2013

Re: Vivado 2016.3 how to know if routing utilization close to full?

@kaza

 

You will find **opt.dcp in <project>/<project>.runs/impl_1 which can be shared to debug the congestion. 

Did you check UG906 and UG949 which covers all the topics for debugging congestion? 

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_3/ug949-vivado-design-methodology.pdf

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_3/ug906-vivado-design-analysis.pdf

 

--Syed

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