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Visitor
Visitor
1,549 Views
Registered: ‎04-18-2018

Vivado 2017.3 write_bit_stream failed with "ERROR: [Designutils 20-1756] VEAM exception in tile CLE_M_X66Y91: Conflicting values 'TRUE' != 'FALSE' for attr 'D_I_USED' in veamRef 'Icle_cle_m_core_X0Y0_

Suddenly after some source file change, my Vivado 2017.3 project failed during write_bit_stream phase with an error message like "ERROR: [Designutils 20-1756] VEAM exception in tile CLE_M_X66Y91: Conflicting values 'TRUE' != 'FALSE' for attr 'D_I_USED' in veamRef 'Icle_cle_m_core_X0Y0_R0/Icle_m/LUTM8'".

 

Another bug?

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Moderator
Moderator
1,530 Views
Registered: ‎03-16-2017

Hi @ugface,

 

Can you share the implementation log file to evaluate it?

 

Are you facing node overlap high values while routing phase ? If yes, then these could be one of the reason for this errors.

 

Regards,

hemangd

Regards,
hemangd

Don't forget to give kudos and mark it as accepted solution if your issue gets resolved.
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Highlighted
Visitor
Visitor
1,521 Views
Registered: ‎04-18-2018

No, I didn't meet congestion issue. Timing was met. Everything seemed fine, except bit file generation.

 

It looked like being related to incremental implementation. After I disabled incremental mode, the problem was solved. It should be a bug in Vivado's handling of incremental mode. Probably, some reuse didn't fully check constraints or updated things consistently.

 

The error message tells inconsistency of property "D_I_USED" of CLE_M_X66Y91.

I checked the implementation log, and found nothing helpful except the error message. After I changed the mode, the old log files were automatically deleted by Vivado.

 

I don't think node overlap or design be the reason. Don't you think it's a bug of the tool?

 

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Moderator
Moderator
1,512 Views
Registered: ‎03-16-2017

Hi @ugface,

 

Okay, 

 

Can you share a testcase to regenerate this error at our end? If by disabling incremental mode the error gets resolved, we may file a CR on it after done a debug on it. First we need to do a debug on it.

 

Regards,

hemangd

Regards,
hemangd

Don't forget to give kudos and mark it as accepted solution if your issue gets resolved.
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Highlighted
Visitor
Visitor
1,506 Views
Registered: ‎04-18-2018

Hi, hemangd,

In my case, the tools only shows the error message above. Nothing helpful else.

I cannot provide you our project files. And I don't know how to design a test case for that. It's not my job to that, right?

I just hope that my submission of these bug cases will help Xilinx to improve its tools.

Within a week, I hit one bug with 2018.1, and now another with 2017.3.

For a company like Xilinx, it's very unreasonable to have too many bugs in the tools, after so many years of development.
Waste a lot of time of your customers for your developer's mistakes.
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Moderator
Moderator
1,461 Views
Registered: ‎01-16-2013

@ugface,

 

If only the incremental run is giving such error message then it looks like a bug to me. Are you seeing the same issue in Vivado 2018.1 for same design? Also which OS are you using? 

It would be very helpful if you can share the design so that we can forward it to the factory and get it fixed. 

 

I can send you a private link so that the design is not shared publically. 

 

--Syed

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Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
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Highlighted
Visitor
Visitor
1,442 Views
Registered: ‎04-18-2018

Before I enabled incremental run, there's no trouble. After I disabled incremental run, trouble disappeared. I didn't get the project implemented in Vivado 2018.1 due to another bug, submitted on another thread.

 

Sorry, I could not share our project design files with you.

 

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Moderator
Moderator
1,401 Views
Registered: ‎01-16-2013

@ugface,

 

Thanks for the update. It would be difficult to report the issue to Factory without design files. We will keep a watch and see if any other user reports such similar issue.  

 

Since you have a solution i.e disabling incremental run, Can you please close this thread by marking your above post as "Accept as Solution". 

 

--Syed

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------
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