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Adventurer
Adventurer
1,069 Views
Registered: ‎08-26-2013

Vivado 2017.4 PBLOCK problem

Hi,

I'm engaged in an Ultrascale FPGA based project with some huge hardware resource same channels. After Constraining with pblocks, during pblock drawing, i have strange problems for defining same size pblocks in some area of FPGA resources. Attached image shows my pblocks. Appending new same-shaped pblocks after third one to two existings yields problems for sizing and placing pblock rectangle. Due to this case, it force me to define some blank place between pblocks and this problem solved. My question is that why this problem arised when we know that FPGA is a Gate Array IC?

 

Thanks for advance

Regards

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3 Replies
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Moderator
Moderator
1,035 Views
Registered: ‎01-16-2013

Re: Vivado 2017.4 PBLOCK problem

@mhmontazeri61

 

Can you please elaborate more on "Appending new same-shaped pblocks after third one to two existings yields problems for sizing and placing pblock rectangle"? Are you seeing any error message? 

 

FYI: https://www.xilinx.com/video/hardware/design-analysis-floorplanning-with-vivado.html

 

--Syed

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Adventurer
Adventurer
926 Views
Registered: ‎08-26-2013

Re: Vivado 2017.4 PBLOCK problem

@syedz,

I have not any problem message but what i see is the splitting pblocks with numbers higher than 3 by vivado tool. It means that tool does not behave same for same pblocks. If i follow a regular way for constraining same vhdl blocks by assigning pblocks, some places do not permit this regularity. This state and the problem with it exactly is my question particularly with a bias that we have a regular array in FPGA.

 

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Moderator
Moderator
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Registered: ‎01-16-2013

Re: Vivado 2017.4 PBLOCK problem

@mhmontazeri61

 

Can you share a test case which replicates the issue? 

 

--Syed

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Give Kudos to a post which you think is helpful and reply oriented.

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