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Participant msauerpb
Participant
1,282 Views
Registered: ‎01-30-2018

Vivado 2017.4 performance with XC7A200TFBG676-2

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Hi,

 

in our design we use an Artix7-200 TFBG676-2. The utilization is 61% LUT, 54% FF, 60% BRAM and 33% DSP. We use a design with 2 microblaze core with separate programes.

A synthetisation run tooks about 45 minutes and an implementation run about 80 minutes. My PC is a Xeon E5-1620 v4 with 32GB RAM. In Vivado 2017.4 I set the maxThread Parameter to 8.

Is the runtime for the complete implementation normal or can I optimize something?

 

Thank you for your help.

BR

martin

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1 Solution

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Xilinx Employee
Xilinx Employee
1,522 Views
Registered: ‎05-08-2012

Re: Vivado 2017.4 performance with XC7A200TFBG676-2

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Hi @msauerpb. While the phase messages are helpful, a full log would give more details that would help in identifying where the run time is coming from.

 

For the synthesis section, the RTL elaboration looks to be the main contributor to the run time. If you find that the console/log pausing for long periods on a certain message that indicates a file, that file could be viewed to see if there is any RTL construct that might take a significant time to synthesize. Also, you might be able to set this section as an out-of-context run, and synthesize separately. This would reduce the global synthesis run time.

 

In the implementation section, I would look for messaging. Do any mention run time? Does the design have significant timing failures? Timing issues and constraints are typical sources of run time.

 


*Please mark replies with the "Accept as solution" option if they are found to be helpful 

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Xilinx Employee
Xilinx Employee
1,239 Views
Registered: ‎01-05-2017

Re: Vivado 2017.4 performance with XC7A200TFBG676-2

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Hi Martin,

 

Can you have a look in your synthesis and implementation log files to see where Vivado is spending the most amount of time. There should be timestamps in the logs to show you how long the tool is spending in the different phases.

Very large number of constraints might be one reason or if you have a lot of wildcards in the constraints - these can impact run times.

 

If you can please share the testcase, constraints or log files if you can so that somebody can have a look.

 

Best Regards,

David

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Participant msauerpb
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1,192 Views
Registered: ‎01-30-2018

Re: Vivado 2017.4 performance with XC7A200TFBG676-2

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Hi,

 

sorry for the late replay. I have to do some other things.

 

I found the following timestamps in the sysnthesis log:

 

---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:27:32 ; elapsed = 00:27:45 . Memory (MB): peak = 3148.746 ; gain = 2747.504
---------------------------------------------------------------------------------

---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:27:54 ; elapsed = 00:28:09 . Memory (MB): peak = 3148.746 ; gain = 2747.504
---------------------------------------------------------------------------------

---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:33:12 ; elapsed = 00:33:19 . Memory (MB): peak = 3942.391 ; gain = 3541.148
---------------------------------------------------------------------------------

---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:35:26 ; elapsed = 00:35:43 . Memory (MB): peak = 3942.391 ; gain = 3541.148
---------------------------------------------------------------------------------

---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:41:14 ; elapsed = 00:41:48 . Memory (MB): peak = 3942.391 ; gain = 3541.148
---------------------------------------------------------------------------------

---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:42:33 ; elapsed = 00:43:11 . Memory (MB): peak = 4034.863 ; gain = 3633.621
---------------------------------------------------------------------------------

---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:43:36 ; elapsed = 00:44:15 . Memory (MB): peak = 4316.230 ; gain = 3914.988
---------------------------------------------------------------------------------

---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:52:51 ; elapsed = 00:53:36 . Memory (MB): peak = 4719.559 ; gain = 4318.316
---------------------------------------------------------------------------------

---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:53:26 ; elapsed = 00:54:12 . Memory (MB): peak = 4719.559 ; gain = 4318.316
---------------------------------------------------------------------------------

---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:53:29 ; elapsed = 00:54:15 . Memory (MB): peak = 4719.559 ; gain = 4318.316
---------------------------------------------------------------------------------

---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:54:15 ; elapsed = 00:55:01 . Memory (MB): peak = 4719.559 ; gain = 4318.316
---------------------------------------------------------------------------------

---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:54:16 ; elapsed = 00:55:02 . Memory (MB): peak = 4719.559 ; gain = 4318.316
---------------------------------------------------------------------------------

---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:54:27 ; elapsed = 00:55:13 . Memory (MB): peak = 4719.559 ; gain = 4318.316
---------------------------------------------------------------------------------

---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:54:29 ; elapsed = 00:55:15 . Memory (MB): peak = 4719.559 ; gain = 4318.316
---------------------------------------------------------------------------------

---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:54:29 ; elapsed = 00:55:15 . Memory (MB): peak = 4719.559 ; gain = 4318.316
---------------------------------------------------------------------------------

 

The timing of the implementation log will follow. I don't know if the constraint files contains wildcard because the code isn't mine. I only have to work with it.

 

Thank your for your help.

BR

martin

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Participant msauerpb
Participant
1,185 Views
Registered: ‎01-30-2018

Re: Vivado 2017.4 performance with XC7A200TFBG676-2

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Hi,

 

the timestamp of the implementation are:

 


    add_files: Time (s): cpu = 00:00:25 ; elapsed = 00:00:28 . Memory (MB): peak = 397.102 ; gain = 167.000
    get_clocks: Time (s): cpu = 00:00:43 ; elapsed = 00:00:34 . Memory (MB): peak = 2411.770 ; gain = 796.395
    link_design: Time (s): cpu = 00:02:32 ; elapsed = 00:02:29 . Memory (MB): peak = 2417.215 ; gain = 2020.113
    Starting DRC Task
        Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 2417.215 ; gain = 0.000
    Starting Logic Optimization Task
        Phase 1: Time (s): cpu = 00:00:34 ; elapsed = 00:02:50 . Memory (MB): peak = 2430.363 ; gain = 13.148
        Phase 2: Time (s): cpu = 00:01:00 ; elapsed = 00:03:13 . Memory (MB): peak = 2434.426 ; gain = 17.211
        Phase 3: Time (s): cpu = 00:01:57 ; elapsed = 00:04:12 . Memory (MB): peak = 2434.426 ; gain = 17.211
        Phase 4: Time (s): cpu = 00:03:07 ; elapsed = 00:05:26 . Memory (MB): peak = 2434.426 ; gain = 17.211
        Phase 5: Time (s): cpu = 00:03:14 ; elapsed = 00:05:32 . Memory (MB): peak = 2434.426 ; gain = 17.211
        Phase 6: Time (s): cpu = 00:03:18 ; elapsed = 00:05:37 . Memory (MB): peak = 2434.426 ; gain = 17.211
    Starting Connectivity Check Task
        Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.369 . Memory (MB): peak = 2434.426 ; gain = 0.000
        Time (s): cpu = 00:03:37 ; elapsed = 00:05:56 . Memory (MB): peak = 2434.426 ; gain = 17.211
    Starting Power Optimization Task
        Pre-processing: Time (s): cpu = 00:01:04 ; elapsed = 00:00:24 . Memory (MB): peak = 3546.227 ; gain = 475.984
        IDT: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.379 . Memory (MB): peak = 3546.227 ; gain = 0.000
        PSMgr Creation: Time (s): cpu = 00:01:39 ; elapsed = 00:00:37 . Memory (MB): peak = 3638.422 ; gain = 568.180
        ODC: Time (s): cpu = 00:00:55 ; elapsed = 00:00:21 . Memory (MB): peak = 3932.613 ; gain = 386.387
        Power optimization passes: Time (s): cpu = 00:02:11 ; elapsed = 00:00:50 . Memory (MB): peak = 3932.613 ; gain = 862.371
        Grouping enables: Time (s): cpu = 00:00:04 ; elapsed = 00:00:06 . Memory (MB): peak = 3932.613 ; gain = 0.000
    Starting PowerOpt Patch Enables Task
        Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 3932.613 ; gain = 0.000
        Power optimization: Time (s): cpu = 00:02:45 ; elapsed = 00:01:22 . Memory (MB): peak = 3932.613 ; gain = 1498.188
        Time (s): cpu = 00:02:45 ; elapsed = 00:01:22 . Memory (MB): peak = 3932.613 ; gain = 1498.188
        opt_design: Time (s): cpu = 00:06:58 ; elapsed = 00:07:43 . Memory (MB): peak = 3932.613 ; gain = 1515.398
        Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.298 . Memory (MB): peak = 3932.613 ; gain = 0.000
        write_checkpoint: Time (s): cpu = 00:01:07 ; elapsed = 00:00:38 . Memory (MB): peak = 3932.613 ; gain = 0.000
        report_drc: Time (s): cpu = 00:00:22 ; elapsed = 00:00:15 . Memory (MB): peak = 3932.613 ; gain = 0.000
        report_utilization: Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 3932.613 ; gain = 0.000
        report_methodology: Time (s): cpu = 00:01:21 ; elapsed = 00:00:48 . Memory (MB): peak = 3932.613 ; gain = 0.000
        report_timing_summary: Time (s): cpu = 00:00:49 ; elapsed = 00:00:32 . Memory (MB): peak = 3932.613 ; gain = 0.000
        PSMgr Creation: Time (s): cpu = 00:00:12 ; elapsed = 00:00:05 . Memory (MB): peak = 4564.426 ; gain = 92.273
        Pre-processing: Time (s): cpu = 00:01:31 ; elapsed = 00:00:38 . Memory (MB): peak = 4849.906 ; gain = 377.754
        IDT: Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 5095.922 ; gain = 239.594
        ODC: Time (s): cpu = 00:00:39 ; elapsed = 00:00:40 . Memory (MB): peak = 5345.184 ; gain = 249.262
        Power optimization passes: Time (s): cpu = 00:02:37 ; elapsed = 00:01:45 . Memory (MB): peak = 5354.176 ; gain = 882.023
        Grouping enables: Time (s): cpu = 00:00:27 ; elapsed = 00:00:33 . Memory (MB): peak = 5354.176 ; gain = 0.000
    Starting PowerOpt Patch Enables Task
        Time (s): cpu = 00:04:44 ; elapsed = 00:02:49 . Memory (MB): peak = 5354.176 ; gain = 0.000
        Power optimization: Time (s): cpu = 00:08:08 ; elapsed = 00:05:29 . Memory (MB): peak = 5354.176 ; gain = 1421.563
    Starting Logic Optimization Task
        Phase 1: Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 5354.176 ; gain = 0.000
        Phase 2: Time (s): cpu = 00:00:28 ; elapsed = 00:00:26 . Memory (MB): peak = 5354.176 ; gain = 0.000
        Phase 3: Time (s): cpu = 00:01:08 ; elapsed = 00:01:06 . Memory (MB): peak = 5354.176 ; gain = 0.000
    Time (s): cpu = 00:01:08 ; elapsed = 00:01:06 . Memory (MB): peak = 5354.176 ; gain = 0.000
    power_opt_design: Time (s): cpu = 00:09:24 ; elapsed = 00:06:42 . Memory (MB): peak = 5354.176 ; gain = 1421.563
    Starting Placer Task
        Phase 1: Time (s): cpu = 00:02:13 ; elapsed = 00:01:49 . Memory (MB): peak = 5354.176 ; gain = 0.000
        Phase 2: Time (s): cpu = 00:05:54 ; elapsed = 00:04:10 . Memory (MB): peak = 5354.176 ; gain = 0.000
        Phase 3: Time (s): cpu = 00:08:32 ; elapsed = 00:06:27 . Memory (MB): peak = 5354.176 ; gain = 0.000
        Phase 4: Time (s): cpu = 00:49:02 ; elapsed = 00:45:55 . Memory (MB): peak = 5354.176 ; gain = 0.000
        place_design: Time (s): cpu = 00:49:22 ; elapsed = 00:46:13 . Memory (MB): peak = 5354.176 ; gain = 0.000
    Starting Physical Synthesis Task
        Phase 1: Time (s): cpu = 00:00:53 ; elapsed = 00:00:25 . Memory (MB): peak = 5354.176 ; gain = 0.000
        Phase 2: Time (s): cpu = 00:01:24 ; elapsed = 00:00:45 . Memory (MB): peak = 5354.176 ; gain = 0.000
        Phase 3: Time (s): cpu = 00:02:04 ; elapsed = 00:01:11 . Memory (MB): peak = 5354.176 ; gain = 0.000
        Phase 4: Time (s): cpu = 00:02:05 ; elapsed = 00:01:12 . Memory (MB): peak = 5354.176 ; gain = 0.000
        Phase 5: Time (s): cpu = 00:02:27 ; elapsed = 00:01:26 . Memory (MB): peak = 5354.176 ; gain = 0.000
        Phase 6: Time (s): cpu = 00:02:27 ; elapsed = 00:01:27 . Memory (MB): peak = 5354.176 ; gain = 0.000
        Phase 7: Time (s): cpu = 00:02:28 ; elapsed = 00:01:27 . Memory (MB): peak = 5354.176 ; gain = 0.000
        Phase 8: Time (s): cpu = 00:02:29 ; elapsed = 00:01:28 . Memory (MB): peak = 5354.176 ; gain = 0.000
        Phase 9: Time (s): cpu = 00:02:29 ; elapsed = 00:01:29 . Memory (MB): peak = 5354.176 ; gain = 0.000
        Phase 10: Time (s): cpu = 00:02:31 ; elapsed = 00:01:30 . Memory (MB): peak = 5354.176 ; gain = 0.000
        Phase 11: Time (s): cpu = 00:02:32 ; elapsed = 00:01:32 . Memory (MB): peak = 5354.176 ; gain = 0.000
        Phase 12: Time (s): cpu = 00:02:33 ; elapsed = 00:01:33 . Memory (MB): peak = 5354.176 ; gain = 0.000
        phys_opt_design: Time (s): cpu = 00:02:57 ; elapsed = 00:01:55 . Memory (MB): peak = 5354.176 ; gain = 0.000
    Starting Routing Task
        Phase 1: Time (s): cpu = 00:02:03 ; elapsed = 00:01:22 . Memory (MB): peak = 5354.176 ; gain = 0.000
        Phase 2: Time (s): cpu = 00:03:49 ; elapsed = 00:02:31 . Memory (MB): peak = 5354.176 ; gain = 0.000
        Phase 3: Time (s): cpu = 00:08:16 ; elapsed = 00:05:06 . Memory (MB): peak = 5354.176 ; gain = 0.000
        Phase 4: Time (s): cpu = 00:19:43 ; elapsed = 00:14:18 . Memory (MB): peak = 5354.176 ; gain = 0.000
        Phase 5: Time (s): cpu = 00:19:57 ; elapsed = 00:14:27 . Memory (MB): peak = 5354.176 ; gain = 0.000
        Phase 6: Time (s): cpu = 00:20:09 ; elapsed = 00:14:35 . Memory (MB): peak = 5354.176 ; gain = 0.000
        Phase 7: Time (s): cpu = 00:20:11 ; elapsed = 00:14:36 . Memory (MB): peak = 5354.176 ; gain = 0.000
        Phase 8: Time (s): cpu = 00:20:11 ; elapsed = 00:14:36 . Memory (MB): peak = 5354.176 ; gain = 0.000
        Phase 9: Time (s): cpu = 00:20:22 ; elapsed = 00:14:48 . Memory (MB): peak = 5354.176 ; gain = 0.000
        Phase 10: Time (s): cpu = 00:20:24 ; elapsed = 00:14:49 . Memory (MB): peak = 5354.176 ; gain = 0.000
        route_design: Time (s): cpu = 00:20:51 ; elapsed = 00:15:05 . Memory (MB): peak = 5354.176 ; gain = 0.000
    Starting Physical Synthesis Task
      Time (s): cpu = 00:11:05 ; elapsed = 00:08:43 . Memory (MB): peak = 5354.176 ; gain = 0.000

 

br

martin

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Xilinx Employee
Xilinx Employee
1,523 Views
Registered: ‎05-08-2012

Re: Vivado 2017.4 performance with XC7A200TFBG676-2

Jump to solution

Hi @msauerpb. While the phase messages are helpful, a full log would give more details that would help in identifying where the run time is coming from.

 

For the synthesis section, the RTL elaboration looks to be the main contributor to the run time. If you find that the console/log pausing for long periods on a certain message that indicates a file, that file could be viewed to see if there is any RTL construct that might take a significant time to synthesize. Also, you might be able to set this section as an out-of-context run, and synthesize separately. This would reduce the global synthesis run time.

 

In the implementation section, I would look for messaging. Do any mention run time? Does the design have significant timing failures? Timing issues and constraints are typical sources of run time.

 


*Please mark replies with the "Accept as solution" option if they are found to be helpful 

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Participant msauerpb
Participant
1,053 Views
Registered: ‎01-30-2018

Re: Vivado 2017.4 performance with XC7A200TFBG676-2

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Hi,

 

I changed the IP blocks to OOC. This reduces the synth. time about 50%.

 

Thank you for the hint.

 

BR

martin

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Moderator
Moderator
1,065 Views
Registered: ‎01-16-2013

Re: Vivado 2017.4 performance with XC7A200TFBG676-2

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@msauerpb,

 

Thanks for the update. If your query is addressed then can you please close this thread by marking the post which answered your query as "Accept as Solution"

 

--Syed

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------
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Moderator
Moderator
1,037 Views
Registered: ‎01-16-2013

Re: Vivado 2017.4 performance with XC7A200TFBG676-2

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@msauerpb,

 

You need to mark the post which has useful information to resolve the issue like the one from @marcb 

You have marked my above post which was suggesting to close this thread. 

 

--Syed

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------
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