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Adventurer
Adventurer
680 Views
Registered: ‎03-04-2018

[Vivado 2018.1] An unexpected error has occurred (11)

Hi, while running P&R I got a crash. The context behind this is that I am attempting to install the Xilinx 1G Ethernet PCS/PMA IP. When I connect the sgmii_clk output from the IP to our MAC (this clock is derived from an external differential 125Mhz gtrefclk):

#
# An unexpected error has occurred (11)
#
Stack:
/lib64/libc.so.6(+0x32510) [0x7ffff5f5f510]
/global/cust_apps/vivado_2018.1/Vivado/2018.1/lib/lnx64.o/librdi_netlist.so(HDLHBusInstTermBit::getBusInstTermLH() const+0x1) [0x7fffc82b3f91]
/global/cust_apps/vivado_2018.1/Vivado/2018.1/lib/lnx64.o/librdi_netlist.so(HDLHBusInstTermBit::getInstanceLH() const+0x9) [0x7fffc82b4119]
/global/cust_apps/vivado_2018.1/Vivado/2018.1/lib/lnx64.o/librdi_timing.so(HAST3TimeAhead::getStaleInstDelays(HSTPtrHashMap<HDLHInstance const, HSTVector<sta::Edge*, std::allocator<sta::Edge*> >*>&)+0x22b) [0x7fffc195052b]
/global/cust_apps/vivado_2018.1/Vivado/2018.1/lib/lnx64.o/librdi_timing.so(HAST3TimeAhead::updateStaleDelays()+0x1a2) [0x7fffc1951bc2]
/global/cust_apps/vivado_2018.1/Vivado/2018.1/lib/lnx64.o/librdi_timing.so(HAST3TimeAhead::updateDelays(HDGUIStatus*, HASTUpdateTimingParams const&)+0x76) [0x7fffc1951f56]
/global/cust_apps/vivado_2018.1/Vivado/2018.1/lib/lnx64.o/librdi_timing.so(HAST3TimeAhead::updateTiming1(HASTUpdateTimingParams const&, HDGUIStatus*)+0x2ae) [0x7fffc19578be]
/global/cust_apps/vivado_2018.1/Vivado/2018.1/lib/lnx64.o/librdi_timing.so(HAST3TimeAhead::updateTiming(HASTUpdateTimingParams const&, HDGUIStatus*)+0x4a0) [0x7fffc19582f0]
/global/cust_apps/vivado_2018.1/Vivado/2018.1/lib/lnx64.o/librdi_implflow.so(HAPSTimingMgr::updateDelays(bool)+0xb8) [0x7fffcb50bfb8]
/global/cust_apps/vivado_2018.1/Vivado/2018.1/lib/lnx64.o/librdi_implflow.so(HAPSPlaceMgrBase::setupTiming()+0x9e) [0x7fffcb4c118e]
/global/cust_apps/vivado_2018.1/Vivado/2018.1/lib/lnx64.o/librdi_implflow.so(HAPSPlaceMgr::incrPlace(HAPSPlaceMgrPlaceConfig)+0x130) [0x7fffcb4b9190]
/global/cust_apps/vivado_2018.1/Vivado/2018.1/lib/lnx64.o/librdi_implflow.so(HAPSPlaceMgr::place(HAPSPlaceMgrPlaceConfig)+0x8b) [0x7fffcb4baedb]
/global/cust_apps/vivado_2018.1/Vivado/2018.1/lib/lnx64.o/librdi_implflow.so(HAPSOptBase::incrPlace(HAPSPlaceMgrPlaceConfig)+0x72) [0x7fffcb6736a2]
/global/cust_apps/vivado_2018.1/Vivado/2018.1/lib/lnx64.o/librdi_implflow.so(HAPSPathLenReduct::optimizeSingleNet(HAPSTimingPath&, HAPSNet*, HDLHElement const*&, bool*)+0x2980) [0x7fffcb6a3cd0]
/global/cust_apps/vivado_2018.1/Vivado/2018.1/lib/lnx64.o/librdi_implflow.so(HAPSFlow::performOptsOnOneNet(HAPSTimingPath&, HDLHNet*, HDLHElement const*&)+0x61f) [0x7fffcb60547f]
/global/cust_apps/vivado_2018.1/Vivado/2018.1/lib/lnx64.o/librdi_implflow.so(HAPSFlow::callPathBasedOpts()+0x1cb5) [0x7fffcb608bb5]
/global/cust_apps/vivado_2018.1/Vivado/2018.1/lib/lnx64.o/librdi_implflow.so(HAPSFlow::optimize()+0x6e8) [0x7fffcb616678]
/global/cust_apps/vivado_2018.1/Vivado/2018.1/lib/lnx64.o/librdi_vivadotasks.so(PhysOptDesignTclTask::phys_opt_design::executeClient()+0xdcd) [0x7fffb42df24d]
/global/cust_apps/vivado_2018.1/Vivado/2018.1/lib/lnx64.o/librdi_vivadotasks.so(PhysOptDesignTclTask::phys_opt_design::execute_()+0x662) [0x7fffb42dfcd2]
/global/cust_apps/vivado_2018.1/Vivado/2018.1/lib/lnx64.o/librdi_vivadotasks.so(PhysOptDesignTclTask::phys_opt_design::execute()+0x96) [0x7fffb42e0246]
/global/cust_apps/vivado_2018.1/Vivado/2018.1/lib/lnx64.o/librdi_common.so(+0x778822) [0x7ffff71da822]
/global/cust_apps/vivado_2018.1/Vivado/2018.1/lib/lnx64.o/libtcl8.5.so(+0x334af) [0x7ffff17434af]
/global/cust_apps/vivado_2018.1/Vivado/2018.1/lib/lnx64.o/libtcl8.5.so(+0x34b38) [0x7ffff1744b38]
/global/cust_apps/vivado_2018.1/Vivado/2018.1/lib/lnx64.o/libtcl8.5.so(Tcl_EvalEx+0x13) [0x7ffff17450a3]
/global/cust_apps/vivado_2018.1/Vivado/2018.1/lib/lnx64.o/libtcl8.5.so(Tcl_FSEvalFileEx+0x1da) [0x7ffff17a9c5a]
/global/cust_apps/vivado_2018.1/Vivado/2018.1/lib/lnx64.o/librdi_commontasks.so(+0x1cf79d) [0x7fffe674c79d]
/global/cust_apps/vivado_2018.1/Vivado/2018.1/lib/lnx64.o/librdi_common.so(+0x778822) [0x7ffff71da822]
/global/cust_apps/vivado_2018.1/Vivado/2018.1/lib/lnx64.o/libtcl8.5.so(+0x334af) [0x7ffff17434af]
/global/cust_apps/vivado_2018.1/Vivado/2018.1/lib/lnx64.o/libtcl8.5.so(Tcl_EvalObjv+0x32) [0x7ffff17435e2]
/global/cust_apps/vivado_2018.1/Vivado/2018.1/lib/lnx64.o/libtcl8.5.so(TclEvalObjEx+0x322) [0x7ffff1745402]
/global/cust_apps/vivado_2018.1/Vivado/2018.1/lib/lnx64.o/librdi_commontasks.so(+0x200ddf) [0x7fffe677dddf]
/global/cust_apps/vivado_2018.1/Vivado/2018.1/lib/lnx64.o/librdi_commontasks.so(+0x2024ae) [0x7fffe677f4ae]
/global/cust_apps/vivado_2018.1/Vivado/2018.1/lib/lnx64.o/librdi_common.so(+0x778822) [0x7ffff71da822]
/global/cust_apps/vivado_2018.1/Vivado/2018.1/lib/lnx64.o/libtcl8.5.so(+0x334af) [0x7ffff17434af]
/global/cust_apps/vivado_2018.1/Vivado/2018.1/lib/lnx64.o/libtcl8.5.so(Tcl_EvalObjv+0x32) [0x7ffff17435e2]
/global/cust_apps/vivado_2018.1/Vivado/2018.1/lib/lnx64.o/libtcl8.5.so(TclEvalObjEx+0x322) [0x7ffff1745402]
/global/cust_apps/vivado_2018.1/Vivado/2018.1/lib/lnx64.o/librdi_commonmain.so(+0x7414) [0x7ffff685e414]
/global/cust_apps/vivado_2018.1/Vivado/2018.1/lib/lnx64.o/libtcl8.5.so(Tcl_Main+0x1d0) [0x7ffff17b0210]
/global/cust_apps/vivado_2018.1/Vivado/2018.1/lib/lnx64.o/librdi_common.so(+0x7bb82b) [0x7ffff721d82b]
/lib64/libpthread.so.0(+0x7aa1) [0x7ffff5d17aa1]
/lib64/libc.so.6(clone+0x6d) [0x7ffff6015bcd]


The failure is consistent across 3 attempts. SOS!

The closest related issue on the forum that i could find is here on an older version of Vivado: https://www.xilinx.com/support/answers/66489.html but I could not find any IOSTANDARD constraints on the gtrefclk in my build.

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3 Replies
Highlighted
Moderator
Moderator
606 Views
Registered: ‎01-16-2013

@silverace99work 

 

For project mode, Please share the runme.log file present in <project>/<project>.runs/impl_1 folder

For non-project mode, share the vivado.log file.

 

If possible can you try in 2018.3 and check if it still crashes? 

 

--Syed

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Did you check our new quick reference timing closure guide (UG1292)?
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Highlighted
Scholar
Scholar
600 Views
Registered: ‎08-07-2014

@silverace99work,

The context behind this is that I am attempting to install the Xilinx 1G Ethernet PCS/PMA IP.

How are you so sure that the reason is dur to this? What is the argument for saying so?

Also did your design pass function verification via simulation?

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Adventurer
Adventurer
587 Views
Registered: ‎03-04-2018

Hi @Syedz. At this point we moved on by moving the ethernet design to another fpga (we are running on a multi-board acceleration platform) and the problem disappeared. The next time I can find time to reproduce the logs, I will do so. Startup life is manic. If in the meantime you would like me to somehow "close" this issue for the moment, please let me know how.


@Anonymous : The single change where I connected the sgmii_clk from the IP to the MAC resulted in this tool crash. If I undo it, the problem goes away. Yes design passes sims.

Thank you for the replies.

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